公开(公告)号：US20060197120A1

公开(公告)日：2006-09-07

申请号：US10550741

申请日：2004-03-23

Applicant: Radu Surdeanu ,  Peter Stolk

Inventor： Radu Surdeanu ,  Peter Stolk

IPC: H01L29/76

CPC classification number: H01L29/4925

Abstract: The present invention provides an MIS type semiconductor device, comprising a semiconductor substrate and a gate electrode formed on the gate insulating film and formed of gate material. The gate electrode comprises: a first layer of activated crystalline gate material having a first side oriented towards a substrate and a second side oriented away from the substrate, the first layer of activated crystalline gate material having a doping level of 1019 ions/cm3 or higher, and a second layer of gate material at the second side of the first layer of activated crystalline gate material. The present invention also provides a method for making such a device.

Abstract translation: 本发明提供了一种MIS型半导体器件，包括半导体衬底和形成在栅极绝缘膜上并由栅极材料形成的栅电极。 所述栅电极包括：第一激活晶体栅极材料层，其具有朝向衬底取向的第一侧和远离所述衬底的第二侧，所述第一激活晶体栅极材料层的掺杂水平为10 19， / SUP>离子/ cm 3以上，第二层栅极材料在第一层激活的结晶栅极材料的第二面。 本发明还提供了制造这种装置的方法。

公开(公告)号：US20050003638A1

公开(公告)日：2005-01-06

申请号：US10497263

申请日：2002-11-20

Applicant: Peter Stolk

Inventor： Peter Stolk

IPC: H01L21/20 ,  H01L21/225 ,  H01L21/265 ,  H01L21/268 ,  H01L21/324 ,  H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L29/786 ,  C30B1/00 ,  H01L21/36

CPC classification number: H01L29/66575 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/268 ,  H01L21/324

Abstract: In the method of manufacturing a semiconductor device (1) with a semiconductor body (2), a doped zone (3) is formed in the semiconductor body (2). The semiconductor body (2) has a crystalline surface region (4), which crystalline surface region (4) is at least partly antorphized so as to form an amorphous surface layer (5). The amorphization is achieved by irradiating the surface (6) with a radiation pulse (7) which is absorbed by the crystalline surface region (4). The radiation pulse (7) has a wavelength which is chosen such that the radiation is absorbed by the crystalline surface region (4), and the energy flux of the radiation pulse (7) is chosen such that the crystal line surface layer (5) is melted. The method is useful for making ultra-shallow junctions.

Abstract translation: 在制造具有半导体本体（2）的半导体器件（1）的方法中，在半导体本体（2）中形成掺杂区（3）。 半导体本体（2）具有晶体表面区域（4），该晶体表面区域（4）至少部分地被去角化，从而形成非晶表面层（5）。 非晶化是通过用由结晶表面区域（4）吸收的辐射脉冲（7）照射表面（6）来实现的。 辐射脉冲（7）具有被选择为使得辐射被结晶表面区域（4）吸收的波长，并且选择辐射脉冲（7）的能量通量使得晶体线表面层（5） 被融化 该方法可用于制造超浅结。

公开(公告)号：US20080169511A1

公开(公告)日：2008-07-17

申请号：US11573346

申请日：2005-08-01

Applicant: Markus Muller ,  Peter Stolk

Inventor： Markus Muller ,  Peter Stolk

IPC: H01L29/78 ,  H01L21/3205

CPC classification number: H01L21/28097 ,  H01L21/823842 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/66545

Abstract: The invention relates to a method of fabricating a CMOS device, comprising providing a semiconductor substrate (101) having therein a layer of insulating material (102), the method comprising providing a layer (106) of a first material over the insulating layer (102), the thickness of the layer (106) of the first material being less in a first region (103) for supporting a first active device than in a second region (104) for supporting a second active device. A layer (107) of a second material is then deposited over the layer (106) of a first material, and the structure is then subjected to a thermal treatment to alloy the first and second materials. The portion of the layers over the first region is entirely alloyed, whereas the portion of the layers over the second region is not, so that a portion (109) of the layer (106) of the first material remains.

Abstract translation: 本发明涉及一种制造CMOS器件的方法，包括提供其中具有绝缘材料层（102）的半导体衬底（101），所述方法包括在所述绝缘层（102）上提供第一材料层（106） ），第一材料的层（106）的厚度在用于支撑第一有源器件的第一区域（103）中比在用于支撑第二有源器件的第二区域（104）中更小。 然后将第二材料的层（107）沉积在第一材料的层（106）上，然后对该结构进行热处理以使第一和第二材料合金化。 第一区域上的层的部分完全合金化，而在第二区域上的部分层不是，使得第一材料的层（106）的一部分（109）保留。

公开(公告)号：US07659154B2

公开(公告)日：2010-02-09

申请号：US11573346

申请日：2005-08-01

Applicant: Markus Muller ,  Peter Stolk

Inventor： Markus Muller ,  Peter Stolk

IPC: H01L21/28 ,  H01L21/44

CPC classification number: H01L21/28097 ,  H01L21/823842 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/66545

Abstract: The invention relates to a method of fabricating a CMOS device, comprising providing a semiconductor substrate (101) having therein a layer of insulating material (102), the method comprising providing a layer (106) of a first material over the insulating layer (102), the thickness of the layer (106) of the first material being less in a first region (103) for supporting a first active device than in a second region (104) for supporting a second active device. A layer (107) of a second material is then deposited over the layer (106) of a first material, and the structure is then subjected to a thermal treatment to alloy the first and second materials. The portion of the layers over the first region is entirely alloyed, whereas the portion of the layers over the second region is not, so that a portion (109) of the layer (106) of the first material remains.

Abstract translation: 本发明涉及一种制造CMOS器件的方法，包括提供其中具有绝缘材料层（102）的半导体衬底（101），所述方法包括在所述绝缘层（102）上提供第一材料层（106） ），第一材料的层（106）的厚度在用于支撑第一有源器件的第一区域（103）中比在用于支撑第二有源器件的第二区域（104）中更小。 然后将第二材料的层（107）沉积在第一材料的层（106）上，然后对该结构进行热处理以使第一和第二材料合金化。 第一区域上的层的部分完全合金化，而在第二区域上的部分层不是，使得第一材料的层（106）的一部分（109）保留。