利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.023 秒)

    On-gate contacts in a MOS device
    4.
    发明授权
    On-gate contacts in a MOS device 有权
    MOS器件中的栅极接点

    公开(公告)号：US08658524B2

    公开(公告)日：2014-02-25

    申请号：US13515758

    申请日：2010-12-02

    申请人： Rainer Herberholz ,  David Vigar

    发明人： Rainer Herberholz ,  David Vigar

    IPC分类号： H01L21/3205

    CPC分类号： H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A MOS device, (400) comprising a semiconductor substrate comprising a channel, an electrode (402) insulated from the channel and positioned at least partly over the channel, and at least one contact (403) to the electrode, the at least one contact being positioned at least partly over the channel.

    摘要翻译： 一种MOS器件（400），包括：包括沟道的半导体衬底，与所述沟道绝缘并且至少部分地位于所述沟道上的电极;以及至少一个接触（403）到所述电极，所述至少一个接触 至少部分地位于通道上方。

    ONE-TIME PROGRAMMABLE CHARGE-TRAPPING NON-VOLATILE MEMORY DEVICE
    5.
    发明申请
    ONE-TIME PROGRAMMABLE CHARGE-TRAPPING NON-VOLATILE MEMORY DEVICE 审中-公开
    一次可编程充电捕获非易失性存储器件

    公开(公告)号：US20110156157A1

    公开(公告)日：2011-06-30

    申请号：US13045754

    申请日：2011-03-11

    申请人： Luca Milani ,  Rainer Herberholz ,  David Vigar

    发明人： Luca Milani ,  Rainer Herberholz ,  David Vigar

    IPC分类号： H01L27/092 ,  H01L21/8238 ,  B05C11/00

    CPC分类号： H01L21/823857 ,  H01L27/0922

    摘要： A one-time programmable (OTP) charge-trapping non-volatile memory (NVM) device is described. In an embodiment, an OTP transistor is formed using a thick gate oxide typically used in producing an I/O MOS transistor and source/drain extensions which are highly doped, shallow and include pocket implants and which are typically used in producing a CORE thin-oxide MOS transistor. In an optimization, the OTP transistor may be formed with two narrow active areas instead of one wider active area. This provides increased performance compared to a device with a wider active area and reduced variability compared to a device with one narrow active area. In another embodiment, a dual gate oxide CMOS technology provides three types of transistor; a thin oxide device, a thick oxide device, and a thick oxide device using the implant type of the thin oxide device for providing an OTP charge-trapping NVM device.

    摘要翻译： 描述了一次性可编程（OTP）电荷捕获非易失性存储器（NVM）器件。 在一个实施例中，OTP晶体管使用通常用于制造I / O MOS晶体管的厚栅极氧化物和高掺杂，浅的并包括袋式注入的源极/漏极延伸部，并且通常用于生产CORE薄膜晶体管， 氧化物MOS晶体管。 在优化中，OTP晶体管可以形成有两个窄的有源区域而不是一个较宽的有源区域。 与具有一个窄有效面积的器件相比，与具有更宽的有源面积的器件相比，具有更低的变化性，这提供了更高的性能。 在另一个实施例中，双栅极氧化物CMOS技术提供三种类型的晶体管; 薄氧化物装置，厚氧化物装置和厚氧化物装置，其使用注入类型的薄氧化物装置来提供OTP电荷俘获NVM装置。

    ON-GATE CONTACTS IN A MOS DEVICE
    6.
    发明申请
    ON-GATE CONTACTS IN A MOS DEVICE 有权
    MOS器件中的门控接点

    公开(公告)号：US20120248512A1

    公开(公告)日：2012-10-04

    申请号：US13515758

    申请日：2010-12-02

    申请人： Rainer Herberholz ,  David Vigar

    发明人： Rainer Herberholz ,  David Vigar

    IPC分类号： H01L29/78 ,  H01L21/336 ,  G06F17/50

    CPC分类号： H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A MOS device, (400) comprising a semiconductor substrate comprising a channel, an electrode (402) insulated from the channel and positioned at least partly over the channel, and at least one contact (403) to the electrode, the at least one contact being positioned at least partly over the channel.

    摘要翻译： 一种MOS器件（400），包括：包括沟道的半导体衬底，与所述沟道绝缘并且至少部分地位于所述沟道上的电极;以及至少一个接触（403）至所述电极，所述至少一个接触 至少部分地位于通道上方。

    IMPROVED METAL-ON-METAL CAPACITOR WITH DIAGONAL FEEDLINE
    8.
    发明申请
    IMPROVED METAL-ON-METAL CAPACITOR WITH DIAGONAL FEEDLINE 有权
    改进金属金属电容器与对角线馈线

    公开(公告)号：US20110199715A1

    公开(公告)日：2011-08-18

    申请号：US13123676

    申请日：2009-09-14

    申请人： Rainer Herberholz

    发明人： Rainer Herberholz

    IPC分类号： H01L27/08 ,  H01G4/33

    CPC分类号： H01L28/91 ,  H01L23/5223 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A design for an improved metal-on-metal capacitor design is described. The design includes a substantially diagonal feedline (411, 412, 413) in each metal layer. Each metal layer (21, 22, 23) comprises two sets of metal fingers which are interleaved. Each set of fingers comprises two subsets of fingers and the subsets of fingers are arranged at right angles to each other. Fingers in a first of the two sets are all connected to the diagonal feedline, whilst fingers in the other set are connected together via fingers at the periphery of the device. The design is repeated in adjacent layers, where the design may be identical or rotated (e.g by 180°) between adjacent metal layers.

    摘要翻译： 描述了一种改进的金属 - 金属电容器设计的设计。 该设计包括在每个金属层中的基本对角线的馈线（411,412,413）。 每个金属层（21,22,23）包括交错的两组金属指。 每组手指包括两个手指子组，并且手指的子集彼此成直角布置。 两组中的第一组中的手指都连接到对角线，而另一组中的手指通过手指在装置的周边连接在一起。 该设计在相邻层中重复，其中设计可以在相邻的金属层之间相同或旋转（例如180°）。

    CONTROL CIRCUITRY FOR MEMORY CELLS
    9.
    发明申请
    CONTROL CIRCUITRY FOR MEMORY CELLS 有权
    记忆细胞的控制电路

    公开(公告)号：US20120314508A1

    公开(公告)日：2012-12-13

    申请号：US13494283

    申请日：2012-06-12

    申请人： Luca Milani ,  Kwangseok Han ,  Rainer Herberholz ,  Justin Penfold

    发明人： Luca Milani ,  Kwangseok Han ,  Rainer Herberholz ,  Justin Penfold

    IPC分类号： G11C16/10

    CPC分类号： G11C17/18 ,  G11C16/0475 ,  G11C17/14 ,  G11C17/146 ,  G11C29/027 ,  G11C29/785 ,  G11C2029/0409 ,  G11C2029/5006 ,  H01L27/11206

    摘要： Control circuitry for memory cells is described. In an embodiment, a breakdown detection circuit is described which is arranged to detect abnormally high currents indicative of a defective cell during programming of a memory cell through monitoring the impedance level at a terminal in the breakdown detection circuit. The breakdown detection circuit is connected between the device being programmed and ground and comprises three transistors, at least one of which is capable of withstanding the programming voltage in case of breakdown. Other embodiments describe a flag bit cell design, a memory array and methods of reading and writing from/to that array, and circuitry for biasing a memory word-line for both read and write operations. The embodiments may be used separately or in a combination.

    摘要翻译： 描述了存储器单元的控制电路。 在一个实施例中，描述了击穿检测电路，其被布置成通过监视击穿检测电路中的端子处的阻抗电平来检测指示存储器单元编程期间的有缺陷单元的异常高电流。 故障检测电路连接在被编程和接地的器件之间，并且包括三个晶体管，其中至少一个能够在击穿的情况下承受编程电压。 其他实施例描述了标志位单元设计，存储器阵列以及从该阵列读取和写入的方法，以及用于偏置读取和写入操作的存储器字线的电路。 实施例可以单独使用或组合使用。

    Single poly non-volatile memory cells
    10.
    发明授权
    Single poly non-volatile memory cells 有权
    单个多晶非易失性存储单元

    公开(公告)号：US09281313B2

    公开(公告)日：2016-03-08

    申请号：US13449822

    申请日：2012-04-18

    申请人： Rainer Herberholz

    发明人： Rainer Herberholz

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11558

    摘要： A non-volatile memory cell that includes a semiconductor substrate; a coupling capacitor located in a first active region of the semiconductor substrate; and at a shared second active region of the semiconductor substrate, a sense transistor and a tunnelling capacitor configured in parallel with the gate of the sense transistor. The coupling capacitor, sense transistor and tunnelling capacitor share a common floating gate electrode and the sense transistor includes source and drain regions arranged such that the tunnelling capacitor is defined by an overlap between the floating gate electrode and the drain region of the sense transistor. Word-line contacts may be to a separate active area from the coupling capacitor. This and/or other features can help to reduce Frenkel-Poole conduction.

    摘要翻译： 一种包括半导体衬底的非易失性存储单元; 位于所述半导体衬底的第一有源区中的耦合电容器; 并且在所述半导体衬底的共享的第二有源区中，与所述读出晶体管的栅极并联配置的检测晶体管和隧道电容器。 耦合电容器，感测晶体管和隧道电容器共用公共浮栅电极，感测晶体管包括排列和漏极区域，使得隧道电容器由感测晶体管的浮置栅电极和漏极区域之间的重叠限定。 字线触点可能与耦合电容器分开的有源区。 这个和/或其他特征可以帮助减少Frenkel-Poole传导。