公开(公告)号：US20080153216A1

公开(公告)日：2008-06-26

申请号：US12071186

申请日：2008-02-19

申请人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

发明人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

IPC分类号： H01L21/82

CPC分类号： H01L29/1608 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/66068 ,  H01L29/8083

摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.

摘要翻译： 碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

公开(公告)号：US06855981B2

公开(公告)日：2005-02-15

申请号：US10230152

申请日：2002-08-29

申请人： Rajesh Kumar ,  Hiroki Nakamura ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

发明人： Rajesh Kumar ,  Hiroki Nakamura ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/66 ,  H01L29/808 ,  H01L29/861 ,  H01L29/866 ,  H01L29/872 ,  H01L29/76

CPC分类号： H01L29/66992 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/866 ,  H01L29/872

摘要： A silicon carbide power device includes a junction field effect transistor and a protective diode, which is a Zener or PN junction diode. The PN junction of the protective diode has a breakdown voltage lower than the PN junction of the transistor. Another silicon carbide power device includes a protective diode, which is a Schottky diode. The Schottky diode has a breakdown voltage lower than the PN junction of the transistor by adjusting Schottky barrier height or the depletion layer formed in the semiconductor included in the Schottky diode. Another silicon carbide power device includes three protective diodes, which are Zener diodes. Two of the protective diodes are used to clamp the voltages applied to the gate and the drain of the transistor due to surge energy and used to release the surge energy. The last diode is a thermo-sensitive diode, with which the temperature of the JFET is measured.

摘要翻译： 碳化硅功率器件包括结场效应晶体管和作为齐纳二极管或PN结二极管的保护二极管。 保护二极管的PN结的击穿电压低于晶体管的PN结。 另一种碳化硅功率器件包括一个保护二极管，它是肖特基二极管。 通过调整肖特基势垒高度或肖特基二极管中包含的半导体中形成的耗尽层，肖特基二极管的击穿电压低于晶体管的PN结。 另一种碳化硅功率器件包括三个保护二极管，它们是齐纳二极管。 两个保护二极管用于钳位由于浪涌能量施加到晶体管的栅极和漏极的电压，并用于释放浪涌能量。 最后一个二极管是热敏二极管，测量JFET的温度。

公开(公告)号：US07355207B2

公开(公告)日：2008-04-08

申请号：US11135661

申请日：2005-05-24

申请人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

发明人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

IPC分类号： H01L29/15 ,  H01L31/0312

CPC分类号： H01L29/1608 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/66068 ,  H01L29/8083

摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.

摘要翻译： 碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

公开(公告)号：US07763504B2

公开(公告)日：2010-07-27

申请号：US12071186

申请日：2008-02-19

申请人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

发明人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

IPC分类号： H01L21/338

CPC分类号： H01L29/1608 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/66068 ,  H01L29/8083

摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.

摘要翻译： 碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

公开(公告)号：US20050258454A1

公开(公告)日：2005-11-24

申请号：US11135661

申请日：2005-05-24

申请人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

发明人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

IPC分类号： H01L21/04 ,  H01L21/336 ,  H01L27/098 ,  H01L27/10 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/808

CPC分类号： H01L29/1608 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/66068 ,  H01L29/8083

摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.

摘要翻译： 碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

公开(公告)号：US20070241338A1

公开(公告)日：2007-10-18

申请号：US11783611

申请日：2007-04-10

申请人： Tsuyoshi Yamamoto ,  Toshio Sakakibara ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ooyanagi ,  Atsuo Watanabe

发明人： Tsuyoshi Yamamoto ,  Toshio Sakakibara ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ooyanagi ,  Atsuo Watanabe

IPC分类号： H01L31/0312

CPC分类号： H01L29/1608 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/8083 ,  H01L29/872

摘要： A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.

摘要翻译： SiC半导体器件包括：具有漏极层，漂移层和源极层的SiC衬底; 多个沟槽穿透源层并到达漂移层; 每个沟槽的侧壁上的栅极层; 覆盖所述栅极层的每个沟槽的侧壁上的绝缘膜; 源极上的源电极; 以及与沟槽接触的沟槽中或下方的二极管部分，以提供二极管。 相邻两个沟槽的侧壁上的栅极层之间的漂移层提供沟道区域。 二极管部分与源电极耦合，并与绝缘膜与栅极层绝缘。

公开(公告)号：US07855384B2

公开(公告)日：2010-12-21

申请号：US11783611

申请日：2007-04-10

申请人： Tsuyoshi Yamamoto ,  Toshio Sakakibara ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ooyanagi ,  Atsuo Watanabe

发明人： Tsuyoshi Yamamoto ,  Toshio Sakakibara ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ooyanagi ,  Atsuo Watanabe

IPC分类号： H01L29/04 ,  H01L29/94

CPC分类号： H01L29/1608 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/8083 ,  H01L29/872

摘要： A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.

摘要翻译： SiC半导体器件包括：具有漏极层，漂移层和源极层的SiC衬底; 多个沟槽穿透源层并到达漂移层; 每个沟槽的侧壁上的栅极层; 覆盖所述栅极层的每个沟槽的侧壁上的绝缘膜; 源极上的源电极; 以及与沟槽接触的沟槽中或下方的二极管部分，以提供二极管。 相邻两个沟槽的侧壁上的栅极层之间的漂移层提供沟道区域。 二极管部分与源电极耦合，并与绝缘膜与栅极层绝缘。

公开(公告)号：US07307313B2

公开(公告)日：2007-12-11

申请号：US11206212

申请日：2005-08-18

申请人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Rajesh Kumar Malhan

发明人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Rajesh Kumar Malhan

IPC分类号： H01L29/76

CPC分类号： H01L29/1066 ,  H01L29/7722 ,  H01L29/8083

摘要： A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.

摘要翻译： 半导体器件包括（a）垂直场效应晶体管，垂直场效应晶体管包括形成在第一导电类型的半导体的第一表面上的漏电极，由半导体的第二表面形成的一对第一沟槽， 沿着第一沟槽分别形成的第二导电类型的控制区域，沿着第一沟槽之间的半导体的第二表面形成的第一导电类型的源极区域，与源极区域连接的源极电极和与源极区域相邻的栅电极 控制区域，（b）与场效应晶体管独立地由半导体的第二表面形成的一对第二沟槽，（c）沿着第二沟槽形成的第二导电类型的控制区，以及（d）二极管， 在第二沟槽之间的第二表面上形成的结。

公开(公告)号：US07173284B2

公开(公告)日：2007-02-06

申请号：US10230115

申请日：2002-08-29

申请人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura

发明人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura

IPC分类号： H01L29/15

CPC分类号： H01L29/66068 ,  H01L29/1608 ,  H01L29/8083 ,  Y10S438/931

摘要： A silicon carbide semiconductor device that includes J-FETs has a drift layer of epitaxially grown silicon carbide having a lower impurity concentration level than a substrate on which the drift layer is formed. Trenches are formed in the surface of the drift layer, and first gate areas are formed on inner walls of the trenches. Second gate areas are formed in isolation from the first gate areas. A source area is formed on channel areas, which are located between the first and second gate areas in the drift layer. A method of manufacturing the device ensures uniform channel layer quality, which allows the device to have a normally-off characteristic, small size, and a low likelihood of defects.

摘要翻译： 包括J-FET的碳化硅半导体器件具有与形成有漂移层的衬底相比杂质浓度水平低的外延生长碳化硅的漂移层。 沟槽形成在漂移层的表面中，并且第一栅极区域形成在沟槽的内壁上。 第二栅极区域与第一栅极区域隔离形成。 源极区域形成在位于漂移层中的第一和第二栅极区域之间的沟道区域上。 制造该器件的方法确保了均匀的沟道层质量，这允许器件具有常规特性，小尺寸和低缺陷可能性。

公开(公告)号：US06551865B2

公开(公告)日：2003-04-22

申请号：US10107174

申请日：2002-03-28

申请人： Rajesh Kumar ,  Hiroki Nakamura ,  Jun Kojima

发明人： Rajesh Kumar ,  Hiroki Nakamura ,  Jun Kojima

IPC分类号： H01L21332

CPC分类号： H01L29/8083 ,  H01L29/1608 ,  Y10S438/931

摘要： Openings are formed in a laminate of a polycrystalline silicon film and an LTO film on a channel layer. While the laminate is used as a mask, impurities are implanted into a place in the channel layer which is assigned to a source region. Also, impurities are implanted into another place in the channel layer which is assigned to a portion of a second gate region. A portion of the polycrystalline silicon film which extends from the related opening is thermally oxidated. The LTO film and the oxidated portion of the polycrystalline silicon film are removed. While a remaining portion of the polycrystalline silicon film is used as a mask, impurities are implanted into a place in the channel layer which is assigned to the second gate region. Accordingly, the source region and the second gate region are formed on a self-alignment basis which suppresses a variation in channel length.