公开(公告)号：US5202287A

公开(公告)日：1993-04-13

申请号：US817048

申请日：1992-01-06

申请人： Rajiv V. Joshi ,  Choon-Sik Oh ,  Dan Moy

发明人： Rajiv V. Joshi ,  Choon-Sik Oh ,  Dan Moy

IPC分类号： H01L21/285 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/76841 ,  Y10S148/025

摘要： Selective deposition of a refractory metal on a silicon substrate utilizing high temperatures and a silane reduction process in which the flow rate ratio of silane to refractory metal halide gas is less than one. In a second embodiment, an additional layer of the refractory metal is deposited utilizing a hydrogen reduction of the metal halide gas at very high temperatures. In both embodiments, a refractory metal barrier layer may be provided by forming a self-aligned refractory metal silicide layer. Alternatively, a two layer self-aligned barrier is formed of a refractory metal silicide lower layer and a refractory metal nitride upper layer and the refractory metal is selectively deposited on the metal nitride.

摘要翻译： 利用高温选择性地在硅衬底上沉积难熔金属，硅烷还原过程中硅烷与难熔金属卤化物气体的流速比小于1。 在第二实施例中，使用在非常高的温度下的金属卤化物气体的氢还原来沉积难熔金属的附加层。 在两个实施例中，可以通过形成自对准难熔金属硅化物层来提供难熔金属阻挡层。 或者，双层自对准屏障由难熔金属硅化物下层和难熔金属氮化物上层形成，难熔金属选择性地沉积在金属氮化物上。

公开(公告)号：US5084417A

公开(公告)日：1992-01-28

申请号：US322486

申请日：1989-03-13

申请人： Rajiv V. Joshi ,  Choon-Sik Oh ,  Dan Moy

发明人： Rajiv V. Joshi ,  Choon-Sik Oh ,  Dan Moy

IPC分类号： H01L21/3205 ,  C23C16/08 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/28518 ,  H01L21/28562 ,  H01L21/76841

摘要： Selective deposition of a refractory metal on a silicon substrate utilizing high temperature and a silane reduction process in which the flow rate ratio of silane to refractory metal halide gas is less than one. In a second embodiment, an additional layer of the refractory metal is deposited utilizing a hydrogen reduction of the metal halide gas at very high temperatures. In both embodiments, a refractory metal barrier layer may be provided by forming a self-aligned refractory metal silicide layer. Alternatively, a two layer self-aligned barrier is formed of a refractory metal silicide lower layer and a refractory metal nitride upper layer and the refractory metal is selectively deposited on the metal nitride.

公开(公告)号：US5221853A

公开(公告)日：1993-06-22

申请号：US763194

申请日：1991-09-20

申请人： Rajiv V. Joshi ,  Choon-Sik Oh ,  Dan Moy

发明人： Rajiv V. Joshi ,  Choon-Sik Oh ,  Dan Moy

IPC分类号： H01L21/285 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/76841 ,  H01L2924/0002

摘要： Selective deposition of a refractory metal on a silicon substrate utilizing high temperatures and a silane reduction process in which the flow rate ratio of silane to refractory metal halide gas is less than one. In a second embodiment, an additional layer of the refractory metal is deposited utilizing a hydrogen reduction of the metal halide gas at very high temperatures. In both embodiments, a refractory metal barrier layer may be provided by forming a self-aligned refractory metal silicide layer. Alternatively, a two layer self-aligned barrier is formed of a refractory metal silicide lower layer and a refractory metal nitride upper layer and the refractory metal is selectively deposited on the metal nitride.

摘要翻译： 利用高温选择性地在硅衬底上沉积难熔金属，硅烷还原过程中硅烷与难熔金属卤化物气体的流速比小于1。 在第二实施例中，使用在非常高的温度下的金属卤化物气体的氢还原来沉积难熔金属的附加层。 在两个实施例中，可以通过形成自对准难熔金属硅化物层来提供难熔金属阻挡层。 或者，双层自对准屏障由难熔金属硅化物下层和难熔金属氮化物上层形成，难熔金属选择性地沉积在金属氮化物上。

公开(公告)号：US06713791B2

公开(公告)日：2004-03-30

申请号：US09770788

申请日：2001-01-26

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Fariborz Assaderaghi ,  Dan Moy ,  Werner Rausch ,  James Culp

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Fariborz Assaderaghi ,  Dan Moy ,  Werner Rausch ,  James Culp

IPC分类号： H01L2974

CPC分类号： H01L27/1027 ,  G11C5/142 ,  G11C11/39

摘要： A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell structure. The method entails simultaneously fabricating a first portion of a T-RAM cell and the n-MOS support device; simultaneously fabricating a second portion of the T-RAM cell and the p-MOS support device; and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices. The first portion of the T-RAM cell is a transfer gate and the second portion of the T-RAM cell is a gated-lateral thyristor storage element. Accordingly, process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS support devices. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc. which are connected to the T-RAM array.

摘要翻译： 提出了具有平面单元结构的T-RAM阵列。 T-RAM阵列包括通过与T-RAM阵列的T-RAM单元共享处理注入步骤制造的n-MOS和p-MOS支持器件。 还提出了一种制造具有平面单元结构的T-RAM阵列的方法。 该方法需要同时制造T-RAM单元和n-MOS支持器件的第一部分; 同时制造T-RAM单元和p-MOS支持装置的第二部分; 并通过将T-RAM单元与p-MOS和n-MOS支持器件相互连接来完成T-RAM单元的制造。 T-RAM单元的第一部分是传输门，并且T-RAM单元的第二部分是门控侧晶闸管存储元件。 因此，制造T-RAM单元的工艺步骤与制造n-MOS和p-MOS支持器件的工艺步骤共享。 n-MOS和p-MOS支持器件是指连接到T-RAM阵列的读出放大器，字线驱动器，列和行解码器等。

公开(公告)号：US4974056A

公开(公告)日：1990-11-27

申请号：US52825

申请日：1987-05-22

申请人： Stephen B. Brodsky ,  Dan Moy ,  Rajiv V. Joshi

发明人： Stephen B. Brodsky ,  Dan Moy ,  Rajiv V. Joshi

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  Y10S257/90

摘要： A gate structure for integrated circuit devices which includes a work function layer, a low resistivity layer, and an electrically conductive barrier layer between the two other layers to prevent the other two layers from intermixing. The work function controlling layer is preferably selected from the group of tungsten, molybdenum, their silicides, or a combination thereof.

公开(公告)号：US08629049B2

公开(公告)日：2014-01-14

申请号：US13420724

申请日：2012-03-15

申请人： Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

发明人： Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

IPC分类号： H01L21/44

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fabrication method for fabricating an electrically programmable fuse method includes depositing a polysilicon layer on a substrate, patterning an anode contact region, a cathode contact region and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, depositing a silicide layer on the polysilicon layer, and forming a plurality of anisometric contacts on the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

摘要翻译： 制造电可编程熔丝法的制造方法包括在衬底上沉积多晶硅层，图案化阳极接触区域，阴极接触区域和将阴极接触区域与阳极接触区域导电连接的熔断体，其可通过应用 编程电流，在多晶硅层上沉积硅化物层，以及在预定构型中分别在阴极接触区域和阳极接触区域的硅化物层上形成多个不规则接触。

公开(公告)号：US20130063202A1

公开(公告)日：2013-03-14

申请号：US13612938

申请日：2012-09-13

申请人： Yan Zun Li ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

发明人： Yan Zun Li ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

IPC分类号： H01L23/544 ,  H01H37/76

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.

摘要翻译： 反熔丝具有一个导电类型的第一和第二半导体区域和它们之间具有相反导电类型的第三半导体区域。 接触第一区域的导电区域在横向于栅极的长尺寸方向的第二方向上具有长尺寸。 反熔丝阳极在第二方向上与第一区域间隔开，并且触点与第二区域连接。 在阳极和接触之间施加编程电压，栅极偏压足以完全导通反熔丝的场效应晶体管操作加热第一区域以向外驱动掺杂剂，导致第一区域的边缘更接近于 并且将第一和第二区域之间的电阻降低一个或多个数量级。

公开(公告)号：US20120161855A1

公开(公告)日：2012-06-28

申请号：US13413192

申请日：2012-03-06

申请人： Dan Moy ,  Stephen Wu ,  Peter Wang ,  Brian W. Messenger ,  Edwin Soler ,  Gabriel Chiulli

发明人： Dan Moy ,  Stephen Wu ,  Peter Wang ,  Brian W. Messenger ,  Edwin Soler ,  Gabriel Chiulli

IPC分类号： H01H37/76

CPC分类号： G11C17/18 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.

摘要翻译： 用于编程电子可编程半导体熔丝的装置将编程电流作为一系列多个脉冲施加到熔丝链路。 将编程电流应用为一系列多个短脉冲提供足够高的编程电流电平，以确保可靠且有效的电迁移，同时避免超过熔丝链的温度限制。

公开(公告)号：US20090128225A1

公开(公告)日：2009-05-21

申请号：US11941308

申请日：2007-11-16

申请人： Dan Moy ,  Stephen Wu ,  Peter Wang ,  Brian W. Messenger ,  Edwin Soler ,  Gabriel Chiulli

发明人： Dan Moy ,  Stephen Wu ,  Peter Wang ,  Brian W. Messenger ,  Edwin Soler ,  Gabriel Chiulli

IPC分类号： H01H37/76

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure for an apparatus for programming an electronically programmable semiconductor fuse. The apparatus applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.

摘要翻译： 一种用于编程电子可编程半导体保险丝的装置的设计结构。 该装置将编程电流作为一系列多个脉冲施加到熔丝链路。 将编程电流应用为一系列多个短脉冲提供足够高的编程电流电平，以确保可靠且有效的电迁移，同时避免超过熔丝链的温度限制。

公开(公告)号：US20140021578A1

公开(公告)日：2014-01-23

申请号：US13552106

申请日：2012-07-18

申请人： Junjing Bao ,  Elbert Emin Huang ,  Yan Zun Li ,  Dan Moy

发明人： Junjing Bao ,  Elbert Emin Huang ,  Yan Zun Li ,  Dan Moy

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5256 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic fuse structure including a first Mx metal comprising a conductive cap, an Mx+1 metal located above the Mx metal, wherein the Mx+1 metal does not comprise a conductive cap, and a via, wherein the via electrically connects the Mx metal to the Mx+1 metal in a vertical orientation.