公开(公告)号：US06504210B1

公开(公告)日：2003-01-07

申请号：US09599484

申请日：2000-06-23

申请人： Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Jack A. Mandelman ,  Viraj Sardesai ,  Mary Elizabeth Weybright

发明人： Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Jack A. Mandelman ,  Viraj Sardesai ,  Mary Elizabeth Weybright

IPC分类号： H01L2976

CPC分类号： H01L29/66583 ,  H01L21/28044 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4941 ,  H01L29/6653 ,  H01L29/66553

摘要： A fully polysilicon encapsulated metal-containing damascene gate structure is provided that is useful in Gigabit DRAM (dynamic random access memory) device. The fully encapsulated metal-containing damascene gate comprises a semiconductor substrate having a gate oxide layer formed on a surface portion of said substrate; a gate polysilicon layer formed on said gate oxide layer; a metal layer formed on said polysilicon layer; and a cap oxide layer formed on said metal layer, wherein said metal layer is completely encapsulated by said polysilicon and oxide layers. The damascene gate structure may also include polysilicon spacers formed on said gate polysilicon layer and said metal layer is encapsulated therein and outer polysilicon sidewalls that are oxidized.

摘要翻译： 提供了一种完全多晶硅封装的含金属镶嵌栅极结构，可用于千兆DRAM（动态随机存取存储器）器件。 完全封装的含金属的镶嵌栅极包括具有形成在所述基板的表面部分上的栅极氧化层的半导体基板; 形成在所述栅极氧化物层上的栅极多晶硅层; 形成在所述多晶硅层上的金属层; 以及形成在所述金属层上的帽氧化层，其中所述金属层被所述多晶硅和氧化物层完全包封。 镶嵌栅极结构还可以包括形成在所述栅极多晶硅层上的多晶硅间隔物，并且所述金属层被封装在其中，并且外部多晶硅侧壁被氧化。

公开(公告)号：US06326260B1

公开(公告)日：2001-12-04

申请号：US09599703

申请日：2000-06-22

申请人： Ramachandra Divakaruni ,  James William Adkisson ,  Mary Elizabeth Weybright ,  Scott Halle ,  Jeffrey Peter Gambino ,  Heon Lee

发明人： Ramachandra Divakaruni ,  James William Adkisson ,  Mary Elizabeth Weybright ,  Scott Halle ,  Jeffrey Peter Gambino ,  Heon Lee

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/823462 ,  H01L27/10873

摘要： A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer. Specifically, the structure comprises a semiconductor substrate having a gate oxide layer formed thereon, said substrate including array regions and support regions, said array regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer formed on said conductor material layer, said nitride cap layer and said conductor material layer having spacers formed on sidewalls thereof and said polysilicon layer having an array oxide layer formed on sidewalls thereof, said spacers being substantially flush with the oxide sidewalls, said support regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer on said conductor material layer, said polysilicon layer having a support oxide layer formed on sidewalls thereof, wherein said array oxide layer has a thickness that is greater than said support oxide layer.

摘要翻译： 提供了一种存储器件结构，其中阵列氧化物层的厚度大于支撑氧化物层的厚度。 具体地，该结构包括其上形成有栅极氧化层的半导体衬底，所述衬底包括阵列区域和支撑区域，所述阵列区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层 形成在所述多晶硅层上的导体材料层和形成在所述导体材料层上的氮化物覆盖层，所述氮化物覆盖层和所述导体材料层具有形成在其侧壁上的隔离物，并且所述多晶硅层具有形成在侧壁上的阵列氧化物层 所述间隔件与氧化物侧壁基本齐平，所述支撑区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层，形成在所述多晶硅层上的导体材料层，以及 所述多晶硅层在所述导体材料层上形成氮化物覆盖层 形成在其侧壁上的支撑氧化物层，其中所述阵列氧化物层的厚度大于所述支撑氧化物层。

公开(公告)号：US06930004B2

公开(公告)日：2005-08-16

申请号：US10604731

申请日：2003-08-13

申请人： Geng Wang ,  Kevin Mcstay ,  Mary Elizabeth Weybright ,  Yujun Li ,  Dureseti Chidambarrao

发明人： Geng Wang ,  Kevin Mcstay ,  Mary Elizabeth Weybright ,  Yujun Li ,  Dureseti Chidambarrao

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8242

CPC分类号： H01L27/10876 ,  H01L21/26586 ,  H01L27/10864 ,  H01L29/1041 ,  H01L29/66537 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/945

摘要： A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle θ+δ with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle θ with respect to vertical of a dopant into the channel below the source.

摘要翻译： 提供了形成深沟槽垂直晶体管的方法。 在掺杂半导体衬底中形成具有侧壁的深沟槽。 半导体衬底在其表面中包括反向漏极区域和沿着侧壁的通道。 漏极区域具有顶层和底层。 反向掺杂的源极区域形成在与通道下方的侧壁并置的衬底中。 栅极氧化层形成在与栅极导体并置的沟槽的侧壁上。 执行将栅极导体凹入低于漏极区域的底部电平的步骤，然后相对于反向掺杂物的垂直角进行成角度的离子注入进入源极区域下方的沟道，并以一定角度进行成角度的离子注入 θ相对于掺杂剂的垂直方向到源下方的通道。