公开(公告)号：US20210326204A1

公开(公告)日：2021-10-21

申请号：US17106663

申请日：2020-11-30

Applicant: Rambus Inc.

Inventor： Frederick A. WARE ,  Brent S. HAUKNESS ,  Lawrence LAI

IPC: G06F11/10

Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

公开(公告)号：US20240036975A1

公开(公告)日：2024-02-01

申请号：US18230403

申请日：2023-08-04

Applicant: Rambus Inc.

Inventor： Frederick A. WARE ,  Brent S. HAUKNESS ,  Lawrence LAI

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1048

Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

公开(公告)号：US20250094280A1

公开(公告)日：2025-03-20

申请号：US18902067

申请日：2024-09-30

Applicant: Rambus Inc.

Inventor： Frederick A. WARE ,  Brent S. HALUKNESS ,  Lawrence LAI

IPC: G06F11/10

Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

公开(公告)号：US20200073756A1

公开(公告)日：2020-03-05

申请号：US16565848

申请日：2019-09-10

Applicant: Rambus Inc.

Inventor： Frederick A. WARE ,  Brent S. HAUKNESS ,  Lawrence LAI

IPC: G06F11/10

Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

公开(公告)号：US20160132241A1

公开(公告)日：2016-05-12

申请号：US15000306

申请日：2016-01-19

Applicant: Rambus Inc.

Inventor： Richard E. PEREGO ,  Pradeep BATRA ,  Steven WOO ,  Lawrence LAI ,  Chi-Ming YEUNG

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/10 ,  G06F13/385 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/251 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C7/1072 ,  G11C14/0018 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

公开(公告)号：US20230086896A1

公开(公告)日：2023-03-23

申请号：US17956516

申请日：2022-09-29

Applicant: Rambus Inc.

Inventor： Frederick A. WARE ,  Brent S. HAUKNESS ,  Lawrence LAI

IPC: G06F11/10

Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

公开(公告)号：US20150270000A1

公开(公告)日：2015-09-24

申请号：US14693759

申请日：2015-04-22

Applicant: Rambus Inc.

Inventor： Richard E. PEREGO ,  Pradeep BATRA ,  Steven WOO ,  Lawrence LAI ,  Chi-Ming YEUNG

IPC: G11C14/00 ,  G06F12/02 ,  G06F12/06 ,  G11C7/10

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/10 ,  G06F13/385 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/251 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C7/1072 ,  G11C14/0018 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Abstract translation: 存储器系统包括将命令和地址传送到主存储器模块的CPU。 该模块包括缓冲电路，用于中继CPU和主存储器之间的命令和数据。 存储器模块还包括嵌入式处理器，其共享对主存储器的访问以支持外围功能，例如图形处理，以改善整体系统性能。 缓冲电路有助于CPU和外围处理器之间的指令和数据通信，以最小化或消除修改CPU的需要，从而减少采用具有集成处理能力的主存储器模块的实际障碍。

公开(公告)号：US20150106560A1

公开(公告)日：2015-04-16

申请号：US14574156

申请日：2014-12-17

Applicant: Rambus Inc.

Inventor： Richard E. PEREGO ,  Pradeep BATRA ,  Steven WOO ,  Lawrence LAI ,  Chi-Ming YEUNG

IPC: G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/10 ,  G06F13/385 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/251 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C7/1072 ,  G11C14/0018 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.