中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.014 seconds)

    INTERFACE CLOCK MANAGEMENT
    1.
    发明公开
    INTERFACE CLOCK MANAGEMENT 审中-公开

    公开(公告)号：US20230350835A1

    公开(公告)日：2023-11-02

    申请号：US18144349

    申请日：2023-05-08

    Applicant: Rambus Inc.

    Inventor： Yuanlong WANG

    IPC: G06F13/42 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237

    CPC classification number: G06F13/4243 ,  G06F1/3206 ,  G06F1/3275 ,  G06F1/3237 ,  Y02D30/50 ,  Y02B70/10 ,  Y02D10/00

    Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

    INTERFACE CLOCK MANAGEMENT
    2.
    发明申请
    INTERFACE CLOCK MANAGEMENT 审中-公开

    公开(公告)号：US20200218686A1

    公开(公告)日：2020-07-09

    申请号：US16734839

    申请日：2020-01-06

    Applicant: Rambus Inc.

    Inventor： Yuanlong WANG

    IPC: G06F13/42 ,  G06F1/3237 ,  G06F1/3206 ,  G06F1/3234

    Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

    INTERFACE CLOCK MANAGEMENT
    5.
    发明申请
    INTERFACE CLOCK MANAGEMENT 有权

    公开(公告)号：US20240403255A1

    公开(公告)日：2024-12-05

    申请号：US18738324

    申请日：2024-06-10

    Applicant: Rambus Inc.

    Inventor： Yuanlong WANG

    IPC: G06F13/42 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237

    Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

    INTERFACE CLOCK MANAGEMENT
    6.
    发明申请
    INTERFACE CLOCK MANAGEMENT 有权

    公开(公告)号：US20220222197A1

    公开(公告)日：2022-07-14

    申请号：US17559975

    申请日：2021-12-22

    Applicant: Rambus Inc.

    Inventor： Yuanlong WANG

    IPC: G06F13/42 ,  G06F1/3237 ,  G06F1/3206 ,  G06F1/3234

    Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

Patent Agency Ranking