-
Patent Agency Ranking
公开(公告)号：US10382023B1
公开(公告)日：2019-08-13
申请号：US15969602
申请日：2018-05-02
Applicant: Rambus Inc.
Inventor： Yue Lu , Jared L. Zerbe
Abstract: A clock generating circuit is operated in a phase-locking mode to generate an output clock signal having a first frequency that is phased-locked with respect to a variable-frequency input clock signal. After a frequency transition in the input clock signal, phase-locking is disabled within the clock generating circuit to transition the output clock signal from the first frequency to a second frequency that lacks phase-alignment with the input clock signal, then a frequency-lock range of the clock generating circuit is adjusted to transition the output clock signal from the second frequency to a third frequency that also lacks phase alignment with the input clock signal. After adjusting the frequency-lock range of the clock generating circuit, phase-locking is re-enabled therein to transition the output clock signal from the third frequency to a fourth frequency that is phase-aligned with the variable-frequency input clock signal.
-
公开(公告)号：US09973177B1
公开(公告)日：2018-05-15
申请号：US15360149
申请日：2016-11-23
Applicant: Rambus Inc.
Inventor： Yue Lu , Jared L. Zerbe
CPC classification number: H03K5/00006 , H03J2200/10 , H03L7/0802 , H03L7/083 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/16 , H03L7/24 , H04L7/033
Abstract: In a clock generating circuit having a plurality of injection-locking oscillators, a first one of the injection-locking oscillators is enabled to output a free-running reference clock signal and a control value is generated based at least in part on a frequency relationship between the free-running reference clock signal and an input timing signal. In accordance with the control value, a selected one of the injection-locking oscillators is enabled to generate an output clock signal that is frequency-locked with respect to the input timing signal.
-
公开(公告)号：US09531391B1
公开(公告)日：2016-12-27
申请号：US14715537
申请日：2015-05-18
Applicant: Rambus Inc.
Inventor： Yue Lu , Jared L. Zerbe
CPC classification number: H03K5/00006 , H03J2200/10 , H03L7/0802 , H03L7/083 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/16 , H03L7/24 , H04L7/033
Abstract: Upon detecting transition of an input timing signal from a non-oscillating state to an oscillating state, a clock generating circuit is switched from a paused mode to an open-loop operating mode to transition an output timing signal of the clock generating circuit from a non-oscillating state to an oscillating state in which the output timing signal oscillates at a free-running frequency. A ratio of a reference frequency of the oscillating-state input timing signal and the free-running frequency of the output timing signal is determined and used to adjust a frequency-lock range of the clock generating circuit. The clock generating circuit is then switched from the open-loop operating state to the closed-loop operating state to frequency-lock the output timing signal with respect to the reference frequency of the input timing signal.
Abstract translation: 当检测到输入定时信号从非振荡状态向振荡状态的转变时，时钟发生电路从暂停模式切换到开环工作模式，以将时钟产生电路的输出定时信号从非 振荡状态到输出定时信号以自由运行频率振荡的振荡状态。 确定振荡状态输入定时信号的参考频率与输出定时信号的自由运行频率的比率，并用于调整时钟发生电路的频率锁定范围。 然后，时钟产生电路从开环工作状态切换到闭环工作状态，以相对于输入定时信号的参考频率对输出定时信号进行频率锁定。
-
公开(公告)号：US08896355B1
公开(公告)日：2014-11-25
申请号：US14172031
申请日：2014-02-04
Applicant: Rambus Inc.
Inventor： Yue Lu , Jared L. Zerbe
CPC classification number: H03K5/00006 , H03J2200/10 , H03L7/0802 , H03L7/083 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/16 , H03L7/24 , H04L7/033
Abstract: A variable-frequency input clock signal and a reference clock signal are compared during a frequency-compare interval to generate a value that indicates a ratio of their frequencies. The frequency-ratio value is then applied to configure a wide-range frequency-locking oscillator for operation with a narrowed input frequency range. Because the narrowed input frequency range is targeted to the input clock frequency, the wide-range oscillator is able to rapidly lock to a frequency multiple of the input clock frequency. Because the frequency-compare interval is also brief, an extremely fast-locking, clock-multiplying operation may be effected over a relatively wide range of input clock frequencies.
Abstract translation: 在频率比较间隔期间比较可变频率输入时钟信号和参考时钟信号，以产生指示其频率比率的值。 然后应用频率比值来配置宽范围的锁频振荡器，以便在输入频率范围变窄的情况下工作。 由于变窄的输入频率范围针对输入时钟频率，因此宽频振荡器能够快速锁定到输入时钟频率的倍数。 因为频率比较间隔也是短暂的，所以在相对宽的输入时钟频率范围内可以实现非常快速锁定的时钟相乘操作。
-
公开(公告)号：US09065628B1
公开(公告)日：2015-06-23
申请号：US14516771
申请日：2014-10-17
Applicant: Rambus Inc.
Inventor： Yue Lu , Jared L. Zerbe
CPC classification number: H03K5/00006 , H03J2200/10 , H03L7/0802 , H03L7/083 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/16 , H03L7/24 , H04L7/033
Abstract: A clock generating circuit is operated in a closed-loop state to generate an output clock signal that is frequency-locked with respect to an oscillatory input signal. Upon detecting a frequency transition in the input signal, the clock generating circuit is switched from the closed-loop operating state to an open-loop operating state to enable the output clock signal to oscillate at a free-running frequency. A ratio between input signal frequency and the free-running frequency of the output clock signal is determined and used to adjust a frequency-lock range of the clock generating circuit. The clock generating circuit is then switched from the open-loop operating state to the closed-loop operating state to frequency-lock the output clock signal with respect to input signal.
Abstract translation: 时钟发生电路以闭环状态工作，以产生相对于振荡输入信号频率锁定的输出时钟信号。 当检测到输入信号中的频率转变时，时钟产生电路从闭环工作状态切换到开环工作状态，使输出时钟信号以自由运行频率振荡。 确定输入信号频率与输出时钟信号的自由运行频率之间的比例，并用于调整时钟发生电路的频率锁定范围。 然后，时钟发生电路从开环工作状态切换到闭环工作状态，以对输入信号频率锁定输出时钟信号。
-
-
-
-
Search Results
5
records
(took 0.016 seconds)
