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    Silicon containing material for patterning polymeric memory element
    1.
    发明授权
    Silicon containing material for patterning polymeric memory element 有权
    含硅材料用于图案化聚合物记忆元件

    公开(公告)号：US06803267B1

    公开(公告)日：2004-10-12

    申请号：US10614484

    申请日：2003-07-07

    申请人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Matthew S. Buynoski ,  Patrick K. Cheung ,  Angela T. Hui ,  Ashok M. Khathuria ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Jane V. Oglesby ,  Terence C. Tong ,  James J. Xie

    发明人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Matthew S. Buynoski ,  Patrick K. Cheung ,  Angela T. Hui ,  Ashok M. Khathuria ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Jane V. Oglesby ,  Terence C. Tong ,  James J. Xie

    IPC分类号： H01L21336

    CPC分类号： H01L27/28 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0018

    摘要： The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.

    摘要翻译： 本发明提供一种制造有机存储器件的方法，其中所述制造方法包括形成下电极，在所述下电极的表面上沉积无源材料，在所述被动材料上施加有机半导体材料，以及将所述有源半导体材料 上电极通过有机半导体材料和被动材料到下电极。 有机半导体材料的图案化是通过在有机半导体上沉积硅基抗蚀剂，照射硅基抗蚀剂的部分并图案化硅基抗蚀剂以除去硅基抗蚀剂的照射部分来实现的。 此后，可以对暴露的有机半导体进行构图，并且可以剥离未照射的硅基抗蚀剂以暴露可用作单电池和多电池存储器件的存储器单元的有机半导体材料。 分区组件可以与存储器件集成，以便于堆叠存储器件和编程，读取，写入和擦除存储器元件。

    Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing
    6.
    发明授权
    Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing 有权
    在平坦化之前通过在金属层上形成可平面化材料层来平坦化集成电路结构的金属填充沟槽的方法

    公开(公告)号：US06417093B1

    公开(公告)日：2002-07-09

    申请号：US09703745

    申请日：2000-10-31

    申请人： James J. Xie ,  Ronald J. Nagahara ,  Jayanthi Pallinti ,  Akihisa Ueno

    发明人： James J. Xie ,  Ronald J. Nagahara ,  Jayanthi Pallinti ,  Akihisa Ueno

    IPC分类号： H01L214763

    CPC分类号： H01L21/3212 ,  H01L21/7684

    摘要： A process for forming an integrated circuit structure wherein trenches and/or vias are formed in a predetermined pattern in a dielectric layer, lined with a barrier layer of a first electrically conductive material, and then filled with a second electrically conductive material, and the structure is then planarized to remove the first and second electrically conductive material from the upper surface of the dielectric layer, wherein the improvements comprise: a) before the planarizing step, forming over the second electrically conductive material a layer of a planarizable material capable of being planarized at about the same rate as the first electrically conductive material; and b) then planarizing the structure to remove: i) the planarizable material; ii) the second electrically conductive material; and iii) the first electrically conductive material; above the upper surface of the dielectric material; whereby the planarizable material above the second electrically conductive material in the trenches protects the second electrically conductive material while the first electrically conductive material is being removed from the upper surface of the dielectric layer by the planarizing step to prevent erosion of the upper surface of the second electrically conductive layer.

    摘要翻译： 一种用于形成集成电路结构的方法，其中沟槽和/或通孔以介电层形成为预定图案，衬有第一导电材料的阻挡层，然后填充有第二导电材料，并且结构 然后被平坦化以从电介质层的上表面去除第一和第二导电材料，其中改进包括：a）在平坦化步骤之前，在第二导电材料上形成能够被平坦化的可平面化材料层 以与第一导电材料大致相同的速率; 然后平面化结构以移除：i）可平面化材料; ii）第二导电材料; 和ii）第一导电材料;在电介质材料的上表面之上;由此沟槽中的第二导电材料上方的可平面化材料保护第二导电材料，同时第一导电材料从第二导电材料的上表面 所述介电层通过所述平坦化步骤来防止所述第二导电层的上表面的侵蚀。

    Semiconductor component and method of manufacture
    7.
    发明授权
    Semiconductor component and method of manufacture 有权
    半导体元件及制造方法

    公开(公告)号：US06927113B1

    公开(公告)日：2005-08-09

    申请号：US10444353

    申请日：2003-05-23

    申请人： Kashmir S. Sahota ,  Jeremy Martin ,  Richard J. Huang ,  James J. Xie

    发明人： Kashmir S. Sahota ,  Jeremy Martin ,  Richard J. Huang ,  James J. Xie

    IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L23/532

    CPC分类号： H01L21/76811 ,  H01L21/76835 ,  H01L21/7684 ,  H01L21/76849 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor component and a method for manufacturing the semiconductor component that mitigates electromigration and stress migration in a metallization system of the semiconductor component. A hardmask is formed over a dielectric layer and an opening is etched through the hardmask and into the dielectric layer. The opening is lined with a barrier layer and filled with an electrically conductive material. The electrically conductive material is planarized, where the planarization process stops on the barrier layer. Following planarization, the electrically conductive material is recessed using either an over-polishing process with highly selective copper slurry or a wet etching process to partially re-open the filled metal-filled trench or via. The recess process is performed such that the exposed portion of the electrically conductive material is below the dielectric layer. A capping layer is then deposited on both the dielectric portion and the exposed metal interconnect portion of the electrically conductive material.

    摘要翻译： 一种半导体部件和用于制造半导体部件的方法，其减轻半导体部件的金属化系统中的迁移和应力迁移。 在介电层上形成硬掩模，并且通过硬掩模蚀刻开口并进入电介质层。 开口衬有阻挡层并填充有导电材料。 导电材料被平坦化，其中平坦化处理在阻挡层上停止。 在平坦化之后，使用具有高选择性铜浆料的过度抛光工艺或湿式蚀刻工艺来使导电材料凹陷，以部分地重新打开填充的填充有金属的沟槽或通孔。 执行凹陷处理，使得导电材料的暴露部分在介电层之下。 然后在电介质部分和导电材料的暴露的金属互连部分上沉积覆盖层。

    Process for selective polishing of metal-filled trenches of integrated circuit structures
    8.
    发明授权
    Process for selective polishing of metal-filled trenches of integrated circuit structures 有权
    用于选择性抛光集成电路结构的金属填充沟槽的工艺

    公开(公告)号：US06503828B1

    公开(公告)日：2003-01-07

    申请号：US09882124

    申请日：2001-06-14

    申请人： Ronald J. Nagahara ,  James J. Xie ,  Akihisa Ueno ,  Jayanthi Pallinti

    发明人： Ronald J. Nagahara ,  James J. Xie ,  Akihisa Ueno ,  Jayanthi Pallinti

    IPC分类号： H01L214763

    CPC分类号： H01L21/3212 ,  H01L21/7684

    摘要： The invention provides a process for selectively polishing a main electrically conductive layer of an integrated circuit structure by the steps of forming a polishing barrier layer over depressed regions of the main electrically conductive layer; and polishing the portion of the main electrically conductive layer not covered by the polishing barrier layer. The integrated circuit structure treated by the process of the invention contains one or more openings in a layer of dielectric material, and the main electrically conductive layer fills the one or more openings such that the depressed regions of the main electrically conductive layer overlie said one or more openings.

    摘要翻译： 本发明提供了一种通过在主导电层的凹陷区域上形成抛光阻挡层的步骤来选择性地研磨集成电路结构的主导电层的工艺; 并且抛光未被抛光阻挡层覆盖的主导电层的部分。 通过本发明的方法处理的集成电路结构在介电材料层中包含一个或多个开口，并且主导电层填充一个或多个开口，使得主导电层的凹陷区域覆盖所述一个或多个 更多开口

    Slurry-less polishing for removal of excess interconnect material during fabrication of a silicon integrated circuit
    9.
    发明授权
    Slurry-less polishing for removal of excess interconnect material during fabrication of a silicon integrated circuit 有权
    在硅集成电路的制造期间，用于去除多余互连材料的无浆抛光

    公开(公告)号：US07141502B1

    公开(公告)日：2006-11-28

    申请号：US10673597

    申请日：2003-09-29

    申请人： James J. Xie ,  Kashmir S. Sahota ,  Richard J. Huang

    发明人： James J. Xie ,  Kashmir S. Sahota ,  Richard J. Huang

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/7684 ,  B24B37/042 ,  H01L21/3212

    摘要： A method for Chemical-Mechanical Polishing utilizes a two step process. The first step utilizes a slurry with abrasive particles which become embedded into a conditioned polishing pad having small cavities in the surface. During the second step the slurry flow is discontinued and the final polishing is performed using the embedded small abrasive particles. Using this method dishing has been reduced considerably, and has enabled the fabrication of a Damascene metal gate NMOSFET fabricated with Atomic Layer Deposition (ALD).

    摘要翻译： 化学机械抛光方法采用两步法。 第一步使用具有磨料颗粒的浆料，该磨料颗粒嵌入到表面上具有小空腔的调理抛光垫中。 在第二步骤期间，浆料流动停止，并且使用嵌入的小磨料颗粒进行最终抛光。 使用该方法，凹陷已经显着减少，并且已经能够制造用原子层沉积（ALD）制造的镶嵌金属栅极NMOSFET。

    Method for CMP endpoint detection
    10.
    发明授权
    Method for CMP endpoint detection 有权
    CMP端点检测方法

    公开(公告)号：US06372524B1

    公开(公告)日：2002-04-16

    申请号：US09946895

    申请日：2001-09-05

    申请人： James J. Xie ,  Jayanthi Pallinti ,  Ronald J. Nagahara

    发明人： James J. Xie ,  Jayanthi Pallinti ,  Ronald J. Nagahara

    IPC分类号： H01L2100

    CPC分类号： H01L22/26

    摘要： A method for planarizing an integrated circuit on a substrate to a target surface of the substrate where at least portions of the target surface are of a first material having a first reflectivity. The substrate is overlaid with a top layer of a second material having a second reflectivity thereby forming an upper surface. Material is removed from the upper surface in a planarizing process, and the first reflectivity and second reflectivity of the upper surface are sensed with multiple wavelengths of electromagnetic radiation. The planarization process is stopped when a ratio of the second reflectivity to the first reflectivity equals a predetermined value.

    摘要翻译： 一种用于将基板上的集成电路平坦化到基板的目标表面的方法，其中目标表面的至少一部分是具有第一反射率的第一材料。 衬底覆盖有具有第二反射率的第二材料的顶层，从而形成上表面。 在平坦化处理中从上表面去除材料，并且利用多个电磁辐射波长来感测上表面的第一反射率和第二反射率。 当第二反射率与第一反射率的比等于预定值时，停止平坦化处理。