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104 条记录 (耗时 0.05 秒)

    Silicon containing material for patterning polymeric memory element
    1.
    发明授权
    Silicon containing material for patterning polymeric memory element 有权
    含硅材料用于图案化聚合物记忆元件

    公开(公告)号：US06803267B1

    公开(公告)日：2004-10-12

    申请号：US10614484

    申请日：2003-07-07

    申请人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Matthew S. Buynoski ,  Patrick K. Cheung ,  Angela T. Hui ,  Ashok M. Khathuria ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Jane V. Oglesby ,  Terence C. Tong ,  James J. Xie

    发明人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Matthew S. Buynoski ,  Patrick K. Cheung ,  Angela T. Hui ,  Ashok M. Khathuria ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Jane V. Oglesby ,  Terence C. Tong ,  James J. Xie

    IPC分类号： H01L21336

    CPC分类号： H01L27/28 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0018

    摘要： The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.

    摘要翻译： 本发明提供一种制造有机存储器件的方法，其中所述制造方法包括形成下电极，在所述下电极的表面上沉积无源材料，在所述被动材料上施加有机半导体材料，以及将所述有源半导体材料 上电极通过有机半导体材料和被动材料到下电极。 有机半导体材料的图案化是通过在有机半导体上沉积硅基抗蚀剂，照射硅基抗蚀剂的部分并图案化硅基抗蚀剂以除去硅基抗蚀剂的照射部分来实现的。 此后，可以对暴露的有机半导体进行构图，并且可以剥离未照射的硅基抗蚀剂以暴露可用作单电池和多电池存储器件的存储器单元的有机半导体材料。 分区组件可以与存储器件集成，以便于堆叠存储器件和编程，读取，写入和擦除存储器元件。

    Etch-back process for capping a polymer memory device
    6.
    发明授权
    Etch-back process for capping a polymer memory device 有权
    用于封盖聚合物存储器件的蚀刻工艺

    公开(公告)号：US07323418B1

    公开(公告)日：2008-01-29

    申请号：US11102004

    申请日：2005-04-08

    申请人： Minh Van Ngo ,  Angela T. Hui ,  Sergey D. Lopatin

    发明人： Minh Van Ngo ,  Angela T. Hui ,  Sergey D. Lopatin

    IPC分类号： H01L21/302

    CPC分类号： G11C13/0016 ,  G11C13/0014 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/1608 ,  H01L45/1683 ,  H01L51/0591

    摘要： The present invention leverages an etch-back process to provide an electrode cap for a polymer memory element. This allows the polymer memory element to be formed within a via embedded in layers formed on a substrate. By utilizing the etch-back process, the present invention provides tiny electrical contacts necessary for the proper functioning of polymer memory devices that utilize the vias. In one instance of the present invention, one or more via openings are formed in a dielectric layer to expose an underlying layer. A polymer layer is then formed within the via on the underlying layer with a top electrode material layer deposited over the polymer layer, filling the remaining portion of the via. Excess portions of the top electrode material are then removed by an etching process to form an electrode cap that provides an electrical contact point for the polymer memory element.

    摘要翻译： 本发明利用回蚀工艺来提供用于聚合物存储元件的电极帽。 这允许聚合物存储元件形成在嵌入在衬底上形成的层中的通孔内。 通过利用回蚀工艺，本发明提供了利用通孔的聚合物存储器件的适当功能所需的微小电触点。 在本发明的一个实例中，在电介质层中形成一个或多个通孔以露出下层。 然后在下层上的通孔内形成聚合物层，其中沉积在聚合物层上的顶部电极材料层填充通孔的剩余部分。 然后通过蚀刻工艺去除顶部电极材料的多余部分以形成提供聚合物存储元件的电接触点的电极帽。

    Method(s) facilitating formation of memory cell(s) and patterned conductive
    7.
    发明授权
    Method(s) facilitating formation of memory cell(s) and patterned conductive 失效
    促进形成记忆体和图案化的导电聚合物膜的方法

    公开(公告)号：US06753247B1

    公开(公告)日：2004-06-22

    申请号：US10285183

    申请日：2002-10-31

    申请人： Uzodinma Okoroanyanwu ,  Suzette K. Pangrle ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Mark S. Chang ,  Ramkumar Subramanian ,  Angela T. Hui

    发明人： Uzodinma Okoroanyanwu ,  Suzette K. Pangrle ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Mark S. Chang ,  Ramkumar Subramanian ,  Angela T. Hui

    IPC分类号： H01L214763

    CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C13/0016 ,  H01L27/285

    摘要： A methodology for forming a memory cell is disclosed, wherein an organic polymer layer is formed over a conductive layer and an electrode layer is formed over the organic polymer layer. A first via is etched into the electrode and organic polymer layers, and a dielectric material is applied over the stack to at least fill in the first via. A second via is then etched into the dielectric material so as to expose and make the electrode layer available as a top electrode. A wordline is then formed over the dielectric material such that the top electrode is connected to the wordline by way of the second via. A memory device formed in accordance with the disclosed methodology includes a top electrode formed over an organic polymer layer, a conductive layer under the organic polymer layer, a via defined by a dielectric material and located above the top electrode, and a wordline formed over the dielectric material such that the top electrode is connected to the wordline by way of the via.

    摘要翻译： 公开了一种用于形成存储单元的方法，其中在导电层上形成有机聚合物层，并且在有机聚合物层上形成电极层。 将第一通孔蚀刻到电极和有机聚合物层中，并且将电介质材料施加到堆叠上以至少填充在第一通孔中。 然后将第二通道蚀刻到电介质材料中，以暴露并使电极层可用作顶部电极。 然后在电介质材料上形成字线，使得顶部电极通过第二通孔连接到字线。 根据所公开的方法形成的存储器件包括形成在有机聚合物层上的顶部电极，有机聚合物层下面的导电层，由电介质材料限定并位于顶部电极之上的通孔，以及形成在上部电极上的字线 电介质材料，使得顶部电极通过通孔连接到字线。

    MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation
    9.
    发明授权
    MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation 有权
    MOS晶体管形成工艺包括用于改善硅化物形成的后间隔蚀刻表面处理

    公开(公告)号：US06171919B2

    公开(公告)日：2001-01-09

    申请号：US09361155

    申请日：1999-07-27

    申请人： Paul R. Besser ,  Minh Van Ngo ,  Simon S. Chan ,  Angela T. Hui

    发明人： Paul R. Besser ,  Minh Van Ngo ,  Simon S. Chan ,  Angela T. Hui

    IPC分类号： H01L21336

    CPC分类号： H01L29/665

    摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.

    摘要翻译： 通过自对准硅化物工艺形成具有减小的或最小的结泄漏的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中在自对准硅化物处理之前除去由用于侧壁间隔物形成的反应等离子体蚀刻而导致的硅衬底表面上的碳质残渣 。 实施例包括通过进行氢离子等离子体处理来除去碳质残渣。