公开(公告)号：US6121148A

公开(公告)日：2000-09-19

申请号：US236978

申请日：1999-01-26

申请人： Rashid Bashir ,  Wipawan Yindeepol

发明人： Rashid Bashir ,  Wipawan Yindeepol

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/765 ,  H01L21/302

CPC分类号： H01L21/76264 ,  H01L21/763 ,  H01L21/765 ,  H01L21/76275 ,  H01L21/76286

摘要： A semiconductor device, polysilicon-contacted trench isolation structure that provides improved electrical isolation stability, a method of operating a polysilicon-contacted trench isolated semiconductor device, and a process for manufacturing a polysilicon-contacted trench isolation structure. The trench isolation structure includes an isolation trench formed in a semiconductor substrate. The isolation trench has a layer of trench lining oxide, a layer of trench lining silicon nitride and a trench fill polysilicon (poly 1) layer. Exposed lateral surfaces of the poly 1, which extend above the trench lining silicon nitride, are contacted to another layer of polysilicon (poly 2). The method of operation includes applying a bias voltage to the trench fill poly 1 layer via poly 2. The process for manufacture includes etching an isolation trench that extends through a layer of field oxide and into a semiconductor substrate. After forming layers of trench lining oxide, trench lining silicon nitride and trench fill poly 1 in the isolation trench, the trench lining silicon nitride is etched back to expose lateral surfaces of the trench fill poly 1. A poly 2 layer is then deposited and makes contact with the exposed lateral surfaces of the trench fill poly 1.

摘要翻译： 提供改善的电隔离稳定性的半导体器件，多晶硅接触沟槽隔离结构，操作多晶硅接触沟槽隔离半导体器件的方法，以及制造多晶硅接触沟槽隔离结构的工艺。 沟槽隔离结构包括形成在半导体衬底中的隔离沟槽。 隔离沟槽具有一层沟槽衬垫氧化物，一层沟槽衬里氮化硅和沟槽填充多晶硅（poly 1）层。 在沟槽衬套氮化硅之上延伸的聚1的暴露的侧表面与另一层多晶硅（聚2）接触。 操作方法包括通过多晶硅2向沟槽填充多晶硅层1施加偏置电压。制造方法包括蚀刻延伸穿过场氧化物层并进入半导体衬底的隔离沟槽。 在形成沟槽衬垫氧化物层之后，沟槽衬里氮化硅和沟槽填充聚合物1在隔离沟槽中，沟槽衬里氮化硅被回蚀刻以暴露沟槽填充聚合物1的侧表面。然后沉积聚二层 与沟槽填充聚1的暴露的侧表面接触。

公开(公告)号：US5811315A

公开(公告)日：1998-09-22

申请号：US816408

申请日：1997-03-13

申请人： Wipawan Yindeepol ,  Joel McGregor ,  Rashid Bashir ,  Kevin Brown ,  Joseph Anthony DeSantis

发明人： Wipawan Yindeepol ,  Joel McGregor ,  Rashid Bashir ,  Kevin Brown ,  Joseph Anthony DeSantis

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/763 ,  H01L21/76

CPC分类号： H01L21/76264 ,  H01L21/32 ,  H01L21/763 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76286 ,  Y10S148/05

摘要： A method of forming and planarizing a deep isolation trench in a silicon-on-insulator (SOI) structure begins with a base semiconductor substrate, a buried insulator layer formed on the base semiconductor substrate, and an active silicon layer formed on the buried insulator layer. First, an ONO layer is formed on the active silicon layer. The ONO layer includes a layer of field oxide, a first layer of silicon nitride and a layer of deposited hardmask oxide. A trench having sidewalls that extend to the buried oxide layer is formed. A layer of trench lining oxide is then formed on the exposed sidewalls of the trench. Then, a second layer of silicon nitride is conformally formed on the substrate. The second nitride layer is then anisotropically etched to remove the nitride from the exposed horizontal surface of the hardmask oxide and the buried oxide in the bottom of the trench, but leaving silicon nitride on the vertical sidewall portions of the hardmask oxide, on the sidewalls of the first nitride layer on the sidewalls of the field oxide and on the trench lining oxide. A layer of polysilicon is then deposited to fill the trench and etched back such that the top surface of the polysilicon substantially corresponds to the top surface of the layer of field oxide. The hardmask oxide layer is then removed and the top surface of the polysilicon layer is oxidized.

摘要翻译： 在绝缘体上硅（SOI）结构中形成和平坦化深隔离沟槽的方法从基底半导体衬底，形成在基底半导体衬底上的掩埋绝缘体层和形成在掩埋绝缘体层上的活性硅层开始 。 首先，在有源硅层上形成ONO层。 ONO层包括场氧化物层，第一氮化硅层和沉积的硬掩模氧化物层。 形成具有延伸到掩埋氧化物层的侧壁的沟槽。 然后在暴露的沟槽的侧壁上形成一层沟槽衬垫氧化物。 然后，在衬底上共形地形成第二层氮化硅。 然后对第二氮化物层进行各向异性蚀刻以从硬掩模氧化物的暴露的水平表面和沟槽底部的掩埋氧化物中除去氮化物，但是将氮化硅留在硬掩模氧化物的垂直侧壁部分上， 场氧化物的侧壁上的第一氮化物层和沟槽衬里氧化物上的第一氮化物层。 然后沉积多晶硅层以填充沟槽并被回蚀，使得多晶硅的顶表面基本上对应于场氧化物层的顶表面。 然后去除硬掩模氧化物层，并且多晶硅层的顶表面被氧化。

公开(公告)号：US06362064B1

公开(公告)日：2002-03-26

申请号：US09063074

申请日：1998-04-21

申请人： Joel M. McGregor ,  Rashid Bashir ,  Wipawan Yindeepol

发明人： Joel M. McGregor ,  Rashid Bashir ,  Wipawan Yindeepol

IPC分类号： H01L21331

摘要： Walkout in high voltage trench isolated semiconductor devices is inhibited by applying a voltage bias signal directly to epitaxial silicon surrounding the device. Voltage applied to the surrounding epitaxial silicon elevates the initial breakdown voltage of the device and eliminates walkout. This is because voltage applied to the surrounding epitaxial silicon reduces the strength of the electric field between the silicon of the device and the surrounding silicon. Specifically, application of a positive voltage bias signal to surrounding epitaxial silicon equal to or more positive than the most positive potential occurring at the collector during normal operation of the device ensures that no walkout will occur.

公开(公告)号：US5914523A

公开(公告)日：1999-06-22

申请号：US24329

申请日：1998-02-17

申请人： Rashid Bashir ,  Wipawan Yindeepol

发明人： Rashid Bashir ,  Wipawan Yindeepol

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/765 ,  H01L23/58

CPC分类号： H01L21/76264 ,  H01L21/763 ,  H01L21/765 ,  H01L21/76275 ,  H01L21/76286

摘要： A semiconductor device, polysilicon-contacted trench isolation- structure that provides improved electrical isolation stability, a method of operating a polysilicon-contacted trench isolated semiconductor device, and a process for manufacturing a polysilicon-contacted trench isolation structure. The trench isolation structure includes an isolation trench formed in a semiconductor substrate. The isolation trench has a layer of trench lining oxide, a layer of trench lining silicon nitride and a trench fill polysilicon (poly 1) layer. Exposed lateral surfaces of the poly 1, which extend above the trench lining silicon nitride, are contacted to another layer of polysilicon (poly 2). The method of operation includes applying a bias voltage to the trench fill poly 1 layer via poly 2. The process for manufacture includes etching an isolation trench that extends through a layer of field oxide and into a semiconductor substrate. After forming layers of trench lining oxide, trench lining silicon nitride and trench fill poly 1 in the isolation trench, the trench lining silicon nitride is etched back to expose lateral surfaces of the trench fill poly 1. A poly 2 layer is then deposited and makes contact with the exposed lateral surfaces of the trench fill poly 1.

摘要翻译： 提供改善的电隔离稳定性的半导体器件，多晶硅接触沟槽隔离结构，操作多晶硅接触沟槽隔离半导体器件的方法，以及用于制造多晶硅接触沟槽隔离结构的工艺。 沟槽隔离结构包括形成在半导体衬底中的隔离沟槽。 隔离沟槽具有一层沟槽衬垫氧化物，一层沟槽衬里氮化硅和沟槽填充多晶硅（poly 1）层。 在沟槽衬套氮化硅之上延伸的聚1的暴露的侧表面与另一层多晶硅（聚2）接触。 操作方法包括通过多晶硅2向沟槽填充多晶硅层1施加偏置电压。制造方法包括蚀刻延伸穿过场氧化物层并进入半导体衬底的隔离沟槽。 在形成沟槽衬垫氧化物层之后，沟槽衬里氮化硅和沟槽填充聚合物1在隔离沟槽中，沟槽衬里氮化硅被回蚀刻以暴露沟槽填充聚合物1的侧表面。然后沉积聚二层 与沟槽填充聚1的暴露的侧表面接触。

公开(公告)号：US06979879B1

公开(公告)日：2005-12-27

申请号：US10835698

申请日：2004-04-30

申请人： Wipawan Yindeepol ,  Andy Strachan

发明人： Wipawan Yindeepol ,  Andy Strachan

IPC分类号： H01L29/00 ,  H01L29/866

CPC分类号： H01L29/866

摘要： In a zener zap diode device and a system for making such a device using a double poly process, p+ and n+regions are formed in a tub by means of p-doped and n-doped polysilicon regions, and a p-n junction is formed between the p+ region and an n-tub or between the n+ region and a p-tub. Cobalt or other refractory metal is reacted with silicon to form a silicide on at least the p-doped polysilicon region. By reverse biasing the p-n junction and establishing a sufficiently high zap current, the silicide can be forced to migrate across the junction to form a silicide bridge thereby selectively shorting out the p-n junction.

摘要翻译： 在齐纳二极管器件和使用双重多晶工艺制造这种器件的系统中，通过p掺杂和n掺杂多晶硅区域在p型阱和n +区中形成p +和n +区，并且在p + p +区域和n型浴缸或n +区域和p型浴缸之间。 钴或其他难熔金属与硅反应以在至少p掺杂多晶硅区域上形成硅化物。 通过反向偏置p-n结并建立足够高的zap电流，可以迫使硅化物跨过结迁移以形成硅化物桥，从而选择性地短路p-n结。

公开(公告)号：US5911109A

公开(公告)日：1999-06-08

申请号：US800012

申请日：1997-02-13

申请人： Reda R. Razouk ,  Kulwant S. Egan ,  Wipawan Yindeepol ,  Waclaw C. Koscielniak

发明人： Reda R. Razouk ,  Kulwant S. Egan ,  Wipawan Yindeepol ,  Waclaw C. Koscielniak

IPC分类号： H01L21/3105 ,  H01L21/334 ,  H01L21/762 ,  H01L21/62

CPC分类号： H01L29/66181 ,  H01L21/3105 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76286

摘要： A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.

摘要翻译： 公开了具有与半导体衬底的表面相交的壁和衬在壁上的氧化/扩散阻挡层的沟槽。 氧化/扩散屏障在沟槽的边缘上延伸，以防止例如沟槽中的应力缺陷和沟槽内的垂直鸟嘴形成。 在沟槽内沉积诸如多晶硅的填充材料，随后在沟槽上沉积平坦化层。 在施加热量之后，平坦化层流动以在沟槽上形成平坦化层。 使用高压磷硅玻璃作平坦化层，平坦化层在低温下适当地流动短时间。

公开(公告)号：US5581110A

公开(公告)日：1996-12-03

申请号：US516114

申请日：1995-08-17

申请人： Reda R. Razouk ,  Kulwant S. Egan ,  Wipawan Yindeepol ,  Waclaw C. Koscielniak

发明人： Reda R. Razouk ,  Kulwant S. Egan ,  Wipawan Yindeepol ,  Waclaw C. Koscielniak

IPC分类号： H01L21/3105 ,  H01L21/334 ,  H01L21/762 ,  H01L27/12

CPC分类号： H01L29/66181 ,  H01L21/3105 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76286

摘要： A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.

摘要翻译： 公开了具有与半导体衬底的表面相交的壁和衬在壁上的氧化/扩散阻挡层的沟槽。 氧化/扩散屏障在沟槽的边缘上延伸，以防止例如沟槽中的应力缺陷和沟槽内的垂直鸟嘴形成。 在沟槽内沉积诸如多晶硅的填充材料，随后在沟槽上沉积平坦化层。 在施加热量之后，平坦化层流动以在沟槽上形成平坦化层。 使用高压磷硅玻璃作平坦化层，平坦化层在低温下适当地流动短时间。