公开(公告)号：US20050018482A1

公开(公告)日：2005-01-27

申请号：US10923320

申请日：2004-08-20

申请人： Raul-Adrian Cemea ,  Khandker Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

发明人： Raul-Adrian Cemea ,  Khandker Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418

摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

摘要翻译： 考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。 第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程 第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。 这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。

公开(公告)号：US20050146931A1

公开(公告)日：2005-07-07

申请号：US11055776

申请日：2005-02-09

申请人： Raul-Adrian Cernea ,  Khandker Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

发明人： Raul-Adrian Cernea ,  Khandker Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418

摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

公开(公告)号：US07046548B2

公开(公告)日：2006-05-16

申请号：US11055776

申请日：2005-02-09

申请人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

发明人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

IPC分类号： G11C16/04

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418

摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

摘要翻译： 考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。 第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程 第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。 这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。

公开(公告)号：US06870768B2

公开(公告)日：2005-03-22

申请号：US10923320

申请日：2004-08-20

申请人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

发明人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418

摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

摘要翻译： 考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。 第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程 第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。 这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。

公开(公告)号：US06781877B2

公开(公告)日：2004-08-24

申请号：US10237426

申请日：2002-09-06

申请人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

发明人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

IPC分类号： G11C1604

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418

摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

摘要翻译： 考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。 第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程 第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。 这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。

公开(公告)号：US20060203561A1

公开(公告)日：2006-09-14

申请号：US11381972

申请日：2006-05-05

申请人： Yan Li ,  Yupin Fong ,  Toru Miwa

发明人： Yan Li ,  Yupin Fong ,  Toru Miwa

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5646

摘要： In a non-volatile memory programming scheme where the memory cells are programmed in two or more sequential programming passes, when there is insufficient host data to program at least some of the memory cells during the second pass, some of the memory cells may be programmed to the wrong threshold voltage. This can be prevented by modifying the programming scheme so that this does not occur. In one implementation, this is accomplished by choosing a code scheme, which does not cause the memory cells to be programmed to the wrong threshold voltage during the second programming pass, or by programming the memory cells in accordance with substitute data that would not cause the cells to be programmed to an erroneous state.

摘要翻译： 在非易失性存储器编程方案中，其中存储器单元被编程在两个或多个顺序编程遍中，当在第二遍期间存在不足的主机数据来编程至少一些存储器单元时，一些存储器单元可被编程 到错误的阈值电压。 这可以通过修改编程方案来避免这样的情况。 在一个实现中，这是通过选择代码方案来实现的，该代码方案不会在第二编程遍期间将存储器单元编程到错误的阈值电压，或者通过根据不会导致 单元被编程为错误状态。

公开(公告)号：US20050237814A1

公开(公告)日：2005-10-27

申请号：US10830824

申请日：2004-04-23

申请人： Yan Li ,  Yupin Fong ,  Toru Miwa

发明人： Yan Li ,  Yupin Fong ,  Toru Miwa

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5646

摘要： In a non-volatile memory programming scheme where the memory cells are programmed in two or more sequential programming passes, when there is insufficient host data to program at least some of the memory cells during the second pass, some of the memory cells may be programmed to the wrong threshold voltage. This can be prevented by modifying the programming scheme so that this does not occur. In one implementation, this is accomplished by choosing a code scheme, which does not cause the memory cells to be programmed to the wrong threshold voltage during the second programming pass, or by programming the memory cells in accordance with substitute data that would not cause the cells to be programmed to an erroneous state.

摘要翻译： 在非易失性存储器编程方案中，其中存储器单元被编程在两个或多个顺序编程遍中，当在第二遍期间存在不足的主机数据来编程至少一些存储器单元时，一些存储器单元可被编程 到错误的阈值电压。 这可以通过修改编程方案来避免这样的情况。 在一个实现中，这是通过选择代码方案来实现的，该代码方案不会在第二编程遍期间将存储器单元编程到错误的阈值电压，或者通过根据不会导致 单元被编程为错误状态。

公开(公告)号：US07602647B2

公开(公告)日：2009-10-13

申请号：US12205918

申请日：2008-09-08

申请人： Yan Li ,  Yupin Fong

发明人： Yan Li ,  Yupin Fong

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).

公开(公告)号：US07522454B2

公开(公告)日：2009-04-21

申请号：US11458997

申请日：2006-07-20

申请人： Yan Li ,  Yupin Fong

发明人： Yan Li ,  Yupin Fong

IPC分类号： G11C11/34

CPC分类号： G11C7/02 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).

摘要翻译： 存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合 ）。 为了补偿该耦合，给定存储器单元的读取或编程过程可以考虑相邻存储器单元的编程状态。 为了确定是否需要补偿，可以执行包括感测关于相邻存储器单元的编程状态的信息（例如，在相邻位线或其它位置上）的处理。

公开(公告)号：US20090003052A1

公开(公告)日：2009-01-01

申请号：US12205918

申请日：2008-09-08

申请人： Yan Li ,  Yupin Fong

发明人： Yan Li ,  Yupin Fong

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).

摘要翻译： 存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合 ）。 为了补偿该耦合，给定存储器单元的读取或编程过程可以考虑相邻存储器单元的编程状态。 为了确定是否需要补偿，可以执行包括感测关于相邻存储器单元的编程状态的信息（例如，在相邻位线或其他位置上）的处理。