公开(公告)号：US07532514B2

公开(公告)日：2009-05-12

申请号：US11848385

申请日：2007-08-31

申请人： Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

发明人： Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3468

摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

摘要翻译： 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。

公开(公告)号：US07443757B2

公开(公告)日：2008-10-28

申请号：US10254898

申请日：2002-09-24

申请人： Raul-Adrian Cernea ,  Yan Li

发明人： Raul-Adrian Cernea ,  Yan Li

IPC分类号： G11C7/00

CPC分类号： G11C7/06 ,  G11C11/5642 ,  G11C16/26

摘要： A memory device and a method thereof allow sensing a plurality of memory cells in parallel while minimizing errors caused by bit-line to bit-line crosstalk. Essentially, the bit line voltages of the plurality of bit line coupled to the plurality of memory cells are controlled such that the voltage difference between each adjacent pair of lines is substantially independent of time while their conduction currents are being sensed. When this condition is imposed, all the alternate currents due to the various bit line capacitance drop out since they all depend on a time varying voltage difference. In another aspect, sensing the memory cell's conduction current is effected by noting its rate of discharging a dedicated capacitor provided in the sense amplifier.

摘要翻译： 存储器件及其方法允许并行地感测多个存储器单元，同时最小化由位线到位线串扰引起的误差。 本质上，耦合到多个存储器单元的多个位线的位线电压被控制，使得每个相邻线对之间的电压差基本上与时间无关，同时它们的传导电流被感测。 当施加这种条件时，由于各种位线电容的所有交流电流都消失，因为它们都取决于时变电压差。 在另一方面，感测存储单元的传导电流通过注意其放大读出放大器中提供的专用电容器的速率来实现。

公开(公告)号：US07428171B2

公开(公告)日：2008-09-23

申请号：US11621750

申请日：2007-01-10

申请人： Raul-Adrian Cernea ,  Yan Li

发明人： Raul-Adrian Cernea ,  Yan Li

IPC分类号： G11C16/06

CPC分类号： G11C7/06 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/28 ,  G11C29/02 ,  G11C29/026 ,  G11C2207/065

摘要： A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.

摘要翻译： 用于减少源极偏置的方法通过具有用于多遍感测的特征和技术的读/写电路来实现。 当并行地检测到一页存储单元时，每次通过有助于识别和关闭具有高于给定分界电流值的传导电流的存储单元。 特别地，在当前通路中的所有感测完成之后，所识别的存储器单元关闭。 以这种方式，关闭操作不会影响感测操作。 在后续通过中的感测将受到源极偏置的影响较小，因为通过消除较高电流单元的贡献，电流流动的总量显着减少。 在感测改进的另一方面，采用参考读出放大器来控制多个读出放大器以减少它们对电源和环境变化的依赖。

公开(公告)号：US20070279992A1

公开(公告)日：2007-12-06

申请号：US11772652

申请日：2007-07-02

申请人： Raul-Adrian Cernea ,  Yan Li

发明人： Raul-Adrian Cernea ,  Yan Li

IPC分类号： G11C11/34

CPC分类号： G11C16/3459 ,  G11C8/08 ,  G11C8/10 ,  G11C11/5628 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3454

摘要： A memory device and a method thereof allow programming and sensing a plurality of memory cells in parallel in order to minimize errors caused by coupling from fields of neighboring cells and to improve performance. The memory device and method have the plurality of memory cells linked by the same word line and a read/write circuit is coupled to each memory cells in a contiguous manner. Thus, a memory cell and its neighbors are programmed together and the field environment for each memory cell relative to its neighbors during programming and subsequent reading is less varying. This improves performance and reduces errors caused by coupling from fields of neighboring cells, as compared to conventional architectures and methods in which cells on even columns are programmed independently of cells in odd columns.

摘要翻译： 存储器件及其方法允许并行编程和感测多个存储器单元，以便最小化由相邻单元的场耦合引起的误差并提高性能。 存储器件和方法具有通过相同字线链接的多个存储器单元，并且读/写电路以连续的方式耦合到每个存储器单元。 因此，存储器单元及其邻居被编程在一起，并且在编程和后续读取期间，每个存储单元相对于其邻居的现场环境变化较小。 与传统架构和偶数列上的单元格独立于奇数列中的单元进行编程的方法相比，这提高了性能并减少了从相邻单元的字段耦合引起的错误。

公开(公告)号：US20070109847A1

公开(公告)日：2007-05-17

申请号：US11621750

申请日：2007-01-10

申请人： Raul-Adrian Cernea ,  Yan Li

发明人： Raul-Adrian Cernea ,  Yan Li

IPC分类号： G11C16/06

CPC分类号： G11C7/06 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/28 ,  G11C29/02 ,  G11C29/026 ,  G11C2207/065

摘要： A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.

摘要翻译： 用于减少源极偏置的方法通过具有用于多遍感测的特征和技术的读/写电路来实现。 当并行地检测到一页存储单元时，每次通过有助于识别和关闭具有高于给定分界电流值的传导电流的存储单元。 特别地，在当前通路中的所有感测完成之后，所识别的存储器单元关闭。 以这种方式，关闭操作不会影响感测操作。 在后续通过中的感测将受到源极偏置的影响较小，因为通过消除较高电流单元的贡献，电流流动的总量显着减少。 在感测改进的另一方面，采用参考读出放大器来控制多个读出放大器以减少它们对电源和环境变化的依赖。

公开(公告)号：US20060227614A1

公开(公告)日：2006-10-12

申请号：US11422034

申请日：2006-06-02

申请人： Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

发明人： Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3468

摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

摘要翻译： 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。

公开(公告)号：US20060221697A1

公开(公告)日：2006-10-05

申请号：US11097517

申请日：2005-04-01

申请人： Yan Li ,  Raul-Adrian Cernea

发明人： Yan Li ,  Raul-Adrian Cernea

IPC分类号： G11C16/04

CPC分类号： G11C16/3468

摘要： A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values by raising the voltage level of the channels of the selected memory cells. A principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.

摘要翻译： 非易失性存储器件包括用于在非易失性存储器中控制多相编程过程的电路。 示例性实施例使用快速通过写入技术，其中使用单个编程遍，但是当存储器单元通过提高所选存储器的通道的电压电平接近其目标值时，选择的存储器单元的偏置被改变为慢编程 细胞。 本发明的一个主要方面引入一个与可读取/写入电路相关联的锁存器，该读取/写入电路可以沿着相应的位线连接到每个选定的存储器单元，以便在该较低级别存储验证结果。

公开(公告)号：US06771536B2

公开(公告)日：2004-08-03

申请号：US10086495

申请日：2002-02-27

申请人： Yan Li ,  Jian Chen ,  Raul-Adrian Cernea

发明人： Yan Li ,  Jian Chen ,  Raul-Adrian Cernea

IPC分类号： G11C1604

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/28 ,  G11C16/3418

摘要： The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.

公开(公告)号：US20120002483A1

公开(公告)日：2012-01-05

申请号：US13236437

申请日：2011-09-19

申请人： Raul-Adrian Cernea ,  Yan Li

发明人： Raul-Adrian Cernea ,  Yan Li

IPC分类号： G11C16/10

CPC分类号： G11C16/3459 ,  G11C8/08 ,  G11C8/10 ,  G11C11/5628 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3454

摘要： A memory device and a method thereof allow programming and sensing a plurality of memory cells in parallel in order to minimize errors caused by coupling from fields of neighboring cells and to improve performance. The memory device and method have the plurality of memory cells linked by the same word line and a read/write circuit is coupled to each memory cells in a contiguous manner. Thus, a memory cell and its neighbors are programmed together and the field environment for each memory cell relative to its neighbors during programming and subsequent reading is less varying. This improves performance and reduces errors caused by coupling from fields of neighboring cells, as compared to conventional architectures and methods in which cells on even columns are programmed independently of cells in odd columns.

摘要翻译： 存储器件及其方法允许并行地编程和感测多个存储器单元，以便最小化由相邻单元的场耦合引起的误差并提高性能。 存储器件和方法具有通过相同字线链接的多个存储器单元，并且读/写电路以连续的方式耦合到每个存储器单元。 因此，存储器单元及其邻居被编程在一起，并且在编程和后续读取期间，每个存储单元相对于其邻居的现场环境变化较小。 与传统架构和偶数列上的单元格独立于奇数列中的单元进行编程的方法相比，这提高了性能并减少了从相邻单元的字段耦合引起的错误。

公开(公告)号：US20110019485A1

公开(公告)日：2011-01-27

申请号：US12900443

申请日：2010-10-07

申请人： Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Lung Chan

发明人： Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Lung Chan

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C11/5642

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.

摘要翻译： 能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。 多个读/写电路被组织成一组类似的组件堆叠。 考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。 处理器由输入逻辑，锁存器和输出逻辑实现。 输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。 输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。 这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。