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    FAST BATCH LOADING AND INCREMENTAL LOADING OF DATA INTO A DATABASE
    1.
    发明申请
    FAST BATCH LOADING AND INCREMENTAL LOADING OF DATA INTO A DATABASE 有权
    快速批量加载和数据加载到数据库中

    公开(公告)号：US20110099155A1

    公开(公告)日：2011-04-28

    申请号：US12984284

    申请日：2011-01-04

    Applicant: James Shau ,  Krishnan Meiyyappan ,  Hung Tran ,  Ravi Krishnamurthy ,  Kapil Surlaker ,  Jeremy Branscome ,  Joseph I. Chamdani

    Inventor： James Shau ,  Krishnan Meiyyappan ,  Hung Tran ,  Ravi Krishnamurthy ,  Kapil Surlaker ,  Jeremy Branscome ,  Joseph I. Chamdani

    IPC: G06F17/30

    CPC classification number: G06F17/30595

    Abstract: Embodiments of the present invention provide for batch and incremental loading of data into a database. In the present invention, the loader infrastructure utilizes machine code database instructions and hardware acceleration to parallelize the load operations with the I/O operations. A large, hardware accelerator memory is used as staging cache for the load process. The load process also comprises an index profiling phase that enables balanced partitioning of the created indexes to allow for pipelined load. The online incremental loading process may also be performed while serving queries.

    Abstract translation: 本发明的实施例提供数据批量和增量加载到数据库中。 在本发明中，装载机基础设施利用机器码数据库指令和硬件加速来将加载操作与I / O操作并行化。 大型的硬件加速器内存用作加载进程的分段缓存。 加载过程还包括一个索引分析阶段，可以对所创建的索引进行平衡分区，以允许流水线负载。 在提供查询时也可以执行在线增量加载过程。

    Systems and methods for managing distributed design chains
    3.
    发明申请
    Systems and methods for managing distributed design chains 审中-公开

    公开(公告)号：US20050278159A1

    公开(公告)日：2005-12-15

    申请号：US10868129

    申请日：2004-06-15

    Applicant: Ravi Krishnamurthy

    Inventor： Ravi Krishnamurthy

    IPC: G06F17/50

    CPC classification number: G06F17/5045

    Abstract: Systems, architectures, and data structures are described which are used to manage distributed design chains, specifically for domains in which data reside in multiple applications and are linked through complex interrelationships. The design chains or design networks integrated by the invention may include multiple companies in multiple sites collaborating to design and develop a new product. The invention is intended to integrate seamlessly and transparently with existing, diverse legacy applications, which include inter-linked data relevant to the design, thereby addressing the needs identified above.

    Computer system for statistical multiplexing of bitstreams
    4.
    发明授权
    Computer system for statistical multiplexing of bitstreams 有权
    用于比特流统计复用的计算机系统

    公开(公告)号：US06754241B1

    公开(公告)日：2004-06-22

    申请号：US09478128

    申请日：2000-01-05

    Applicant: Ravi Krishnamurthy ,  Sriram Sethuraman ,  Xiaobing Lee ,  Tihao Chiang

    Inventor： Ravi Krishnamurthy ,  Sriram Sethuraman ,  Xiaobing Lee ,  Tihao Chiang

    IPC: H04J302

    CPC classification number: H04N21/23655 ,  H04N19/115 ,  H04N19/14 ,  H04N19/15 ,  H04N19/152 ,  H04N19/159 ,  H04N19/172 ,  H04N19/177 ,  H04N19/179 ,  H04N19/42 ,  H04N19/61 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/4347

    Abstract: A PC-type computer has a system bus (e.g., a PCI bus) configured with a main CPU board, a statistical multiplexing (stat-mux) board, and a plurality of video/audio encoder boards, each configured to receive and compress a corresponding video/audio stream. The stat-mux board performs statistical multiplexing on the different compressed bitstreams to transmit multiple bitstreams over individual shared communication channels. Although each of the boards is configured to the system bus, each encoder board has a digital signal processor (DSP) with a synchronized serial interface (SSI) output port that is directly connected to an SSI input port on a DSP on the stat-mux board (which, in one embodiment, has four such DSPs each with six such SSI input ports). As such, (up to 24) compressed video/audio bitstreams generated on the various encoder boards can be transmitted directly to the stat-mux board without having to go through the system bus. In this way, the computer system can provide statistical multiplexing of low-latency video/audio bitstreams without having to suffer the processing delays associated with conventional transmission over PCI system buses.

    Abstract translation: PC型计算机具有配置有主CPU板，统计复用（stat-mux）板和多个视频/音频编码器板的系统总线（例如，PCI总线），每个配置用于接收和压缩 相应的视频/音频流。 统计复用板对不同的压缩比特流执行统计复用，以在各个共享通信信道上传输多个比特流。 虽然每个板都配置为系统总线，但每个编码器板都有一个数字信号处理器（DSP），具有同步的串行接口（SSI）输出端口，它直接连接到数模转换器上的DSP上的SSI输入端口 板（在一个实施例中，具有四个这样的DSP，每个具有六个这样的SSI输入端口）。 因此，在各种编码器板上生成的（多达24个）压缩视频/音频比特流可以直接发送到统一复用板，而不必通过系统总线。 以这种方式，计算机系统可以提供低延迟视频/音频比特流的统计复用，而不必忍受与PCI系统总线上的常规传输相关联的处理延迟。

    Treating non-zero quantized transform coefficients as zeros during video compression processing
    6.
    发明授权
    Treating non-zero quantized transform coefficients as zeros during video compression processing 失效
    在视频压缩处理期间将非零量化变换系数作为零进行处理

    公开(公告)号：US06263021B1

    公开(公告)日：2001-07-17

    申请号：US09262042

    申请日：1999-03-04

    Applicant: Sriram Sethuraman ,  Ravi Krishnamurthy

    Inventor： Sriram Sethuraman ,  Ravi Krishnamurthy

    IPC: H04N712

    CPC classification number: H04N19/69 ,  G06T9/005 ,  H04N19/107 ,  H04N19/126 ,  H04N19/132 ,  H04N19/149 ,  H04N19/15 ,  H04N19/152 ,  H04N19/154 ,  H04N19/162 ,  H04N19/17 ,  H04N19/176 ,  H04N19/192 ,  H04N19/196 ,  H04N19/198 ,  H04N19/30 ,  H04N19/503 ,  H04N19/523 ,  H04N19/587 ,  H04N19/60 ,  H04N19/61 ,  H04N19/66 ,  H04N19/68 ,  H04N19/895

    Abstract: During video coding, a transform such as a discrete cosine transform (DCT) is applied to blocks of image data (e.g., motion-compensated interframe pixel differences) and the resulting transform coefficients for each block are quantized at a specified quantization level. Notwithstanding the fact that some coefficients are quantized to non-zero values, at least one non-zero quantized coefficient is treated as if it had a value of zero for purposes of further processing (e.g., run-length encoding (RLE) the quantized data). When segmentation analysis is performed to identify two or more different regions of interest in each frame, the number of coefficients that are treated as having a value of zero for RLE is different for different regions of interest (e.g., more coefficients for less-important regions). In this way, the number of bits used to encode image data are reduced to satisfy bit rate requirements without (1) having to drop frames adaptively, while (2) conforming to constraints that may be imposed on the magnitude of change in quantization level from frame to frame.

    Abstract translation: 在视频编码期间，将诸如离散余弦变换（DCT）的变换应用于图像数据块（例如，运动补偿帧间像素差异），并且以指定的量化级量对每个块的所得到的变换系数进行量化。 尽管有些系数被量化为非零值，但是为了进一步处理（例如，游程长度编码（RLE））量化数据，至少一个非零量化系数被视为具有零值 ）。 当执行分割分析以识别每个帧中的两个或更多个不同的感兴趣区域时，针对不同的感兴趣区域被视为具有值为零的RLE的系数的数量是不同的（例如，对于不太重要的区域，更多的系数 ）。 以这种方式，减少用于对图像数据进行编码的位数，以满足比特率要求，而不需要（1）必须自适应丢帧，而（2）符合可能对​​量化级别的变化幅度施加的约束 帧到帧

    ACCESSING DATA IN COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE DATA STRUCTURES
    7.
    发明申请
    ACCESSING DATA IN COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE DATA STRUCTURES 审中-公开
    基于硬件兼容数据结构的数据库存储数据库

    公开(公告)号：US20110246432A1

    公开(公告)日：2011-10-06

    申请号：US13107399

    申请日：2011-05-13

    Applicant: Liuxi Yang ,  Kapil Surlaker ,  Ravi Krishnamurthy ,  Michael Corwin ,  Jeremy Branscome ,  Krishnan Meiyyappan ,  Joseph I. Chamdani

    Inventor： Liuxi Yang ,  Kapil Surlaker ,  Ravi Krishnamurthy ,  Michael Corwin ,  Jeremy Branscome ,  Krishnan Meiyyappan ,  Joseph I. Chamdani

    IPC: G06F17/30

    CPC classification number: G06F17/30315

    Abstract: Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups.

    Abstract translation: 本发明的实施例提供了一个或多个能够有效地加速数据库操作的硬件友好的数据结构。 特别地，本发明采用数据库的列存储格式。 在数据库中，列组通过列跳转和用于添加新数据的堆结构存储隐式行ids（RID）和具有列存储和行存储优势的RID至主键列。 固定宽度列压缩允许直接对压缩数据进行硬件数据库处理。 使用全局数据库虚拟地址空间，允许对数据的任何物理地址的算术推导，而不管其位置如何。 还提供了具有令牌比较和排序索引的单词压缩字典，以允许对文本进行高效的基于硬件的搜索。 还提供了一个元组重建过程，允许硬件通过将来自多个列组的数据进行拼接来重建行。

    ACCESSING DATA IN A COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE DATA STRUCTURES
    8.
    发明申请
    ACCESSING DATA IN A COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE DATA STRUCTURES 有权
    基于硬件兼容的数据结构访问存储库数据库中的数据

    公开(公告)号：US20090254532A1

    公开(公告)日：2009-10-08

    申请号：US12099131

    申请日：2008-04-07

    Applicant: Liuxi Yang ,  Kapil Surlaker ,  Ravi Krishnamurthy ,  Michael Corwin ,  Jeremy Branscome ,  Krishnan Meiyyappan ,  Joseph I. Chamdani

    Inventor： Liuxi Yang ,  Kapil Surlaker ,  Ravi Krishnamurthy ,  Michael Corwin ,  Jeremy Branscome ,  Krishnan Meiyyappan ,  Joseph I. Chamdani

    IPC: G06F7/00 ,  G06F17/30

    CPC classification number: G06F17/30315

    Abstract: Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups.

    Abstract translation: 本发明的实施例提供了一个或多个能够有效地加速数据库操作的硬件友好的数据结构。 特别地，本发明采用数据库的列存储格式。 在数据库中，列组通过列跳转和用于添加新数据的堆结构存储隐式行ids（RID）和RID至主键列，具有列存储和行存储优势。 固定宽度列压缩允许直接对压缩数据进行硬件数据库处理。 使用全局数据库虚拟地址空间，允许对数据的任何物理地址的算术推导，而不管其位置如何。 还提供了具有令牌比较和排序索引的单词压缩字典，以允许对文本进行高效的基于硬件的搜索。 还提供了一个元组重建过程，允许硬件通过将来自多个列组的数据进行拼接来重建行。

    Processing elements of a hardware accelerated reconfigurable processor for accelerating database operations and queries
    9.
    发明申请
    Processing elements of a hardware accelerated reconfigurable processor for accelerating database operations and queries 审中-公开
    处理硬件加速可重构处理器的元素，用于加速数据库操作和查询

    公开(公告)号：US20080189251A1

    公开(公告)日：2008-08-07

    申请号：US11895997

    申请日：2007-08-27

    Applicant: Jeremy Branscome ,  Michael Corwin ,  Liuxi Yang ,  James Shau ,  Ravi Krishnamurthy ,  Joseph I. Chamdani

    Inventor： Jeremy Branscome ,  Michael Corwin ,  Liuxi Yang ,  James Shau ,  Ravi Krishnamurthy ,  Joseph I. Chamdani

    IPC: G06F17/30

    CPC classification number: G06F16/2453

    Abstract: Embodiments of the present invention provide processing elements that are capable of performing high level database operations in hardware based on machine code instructions. These processing elements employ a dataflow architecture that operates on data in hardware without interruption or software. A scanning/indexing processing element may comprise logic that analyze database column groups stored in local memory, perform parallel field extraction and comparison, and generates a list of row pointers (row ids or RIDs) referencing those rows whose value(s) satisfy an applied predicate. The scanning/indexing processing may also be used to project database column groups, search and join index structures, and manipulate in-flight metadata flows, composing, merging, reducing, and modifying multi-dimensional lists of intermediate and final results. Furthermore, a scanning/indexing processing element may be used for joins with indexes, like a Group Index, which involves the association of each input tuple with potentially many related data components, in a one-to-many mapping. An XCAM processing element may comprise logic to perform associative database operations, like accumulation and aggregation, sieving, sorting and associative joins.

    Abstract translation: 本发明的实施例提供了能够基于机器码指令在硬件中执行高级数据库操作的处理元件。 这些处理元件采用在不中断或软件的情况下对硬件上的数据进行操作的数据流架构。 扫描/索引处理元件可以包括分析存储在本地存储器中的数据库列组，执行并行字段提取和比较的逻辑，并且生成参考其值满足应用的那些行的行指针（行ID或RID）的列表 谓词。 扫描/索引处理也可用于投影数据库列组，搜索和连接索引结构，以及操纵机上元数据流，组合，合并，减少和修改中间和最终结果的多维列表。 此外，扫描/索引处理元件可以用于具有诸如组索引的索引的连接，该索引涉及每个输入元组与潜在的许多相关数据组件的关联，在一对多映射中。 XCAM处理元件可以包括执行关联数据库操作的逻辑，例如累积和聚合，筛选，排序和关联连接。

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