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公开(公告)号：US06665828B1
公开(公告)日：2003-12-16
申请号：US09664848
申请日：2000-09-19
IPC分类号： G01R3128
CPC分类号： G01R31/318555 , G01R31/318385 , G01R31/318536
摘要： A method and system for testing an integrated circuit (IC) comprising a plurality of logic units and a plurality of level sensitive scan design latches (LSSD) chains (scan chains) where the partitioning of the scan chains is different than the partitioning of the logic units. Scan blocks, each scan block comprising multiplexers, a pseudo random pattern generator (PRPG), a partitioned multiple input shift register (MISR), functional logic and control function logic are distributively placed around and close to scan inputs and scan outputs of the IC in otherwise unused area too small for larger functional logic blocks. The MISR, which contains many loaded latches and other logic, would normally be the largest element of the scan block has been partitioned into a sub-set of a full MISR to minimize the size of an individual scan block. The scan block has the functionality to enable LSSD testing, system testing and logic built in self test (LBIST) by the way the individual scan blocks are wired to the scan inputs and scan outputs of the logic units within the IC. Two or more scan blocks are needed to make a complete MISR depending on the sub-set partitioning of the MISR in each scan block. Scan block may have particular IC scan inputs and scan outputs wired into many different multiplexer inputs maintaining a known testability so wiring at the local level may be optimized. Since most of the wiring to the logic unit scan chains, wiring to the central scan switch is minimized reducing wiring complexity and cost. By partitioning the MISR, the size of the standardized Scan blocks is minimized allowing the most effective placement around logic units.
摘要翻译： 一种用于测试集成电路（IC）的方法和系统，该集成电路（IC）包括多个逻辑单元和多个电平敏感扫描设计锁存器（LSSD）链（扫描链），其中扫描链的划分不同于逻辑的分割 单位。 扫描块，包括多路复用器的每个扫描块，伪随机模式发生器（PRPG），分区多输入移位寄存器（MISR），功能逻辑和控制功能逻辑分布放置在IC的扫描输入和扫描输出周围并靠近 否则对于较大的功能逻辑块，未使用的区域太小。 包含许多加载锁存器和其他逻辑的MISR通常将被扫描块的最大元素划分成完整MISR的子集，以最小化单个扫描块的大小。 扫描块具有通过各个扫描块连接到IC内的逻辑单元的扫描输入和扫描输出的方式来启用LSSD测试，内部自检（LBIST）中的LSSD测试和逻辑功能。 需要两个或更多个扫描块来根据每个扫描块中的MISR的子集划分来完成MISR。 扫描块可能具有特定的IC扫描输入和连接到许多不同的多路复用器输入中的扫描输出，保持已知的可测试性，从而可以优化在局部级别的布线。 由于大多数逻辑单元的接线扫描链，所以将中央扫描开关的接线最小化，从而降低了布线的复杂性和成本。 通过划分MISR，可以将标准化的扫描块的大小最小化，从而最有效地放置在逻辑单元周围。
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公开(公告)号：US6006311A
公开(公告)日：1999-12-21
申请号：US839559
申请日：1997-04-14
CPC分类号： G11C29/88 , G06F12/126 , G11C29/76 , G06F2212/1032
摘要： A method of dynamically avoiding defective cache lines in a cache used by a processor of a computer system is disclosed. A repair mask is used, having an array of bit fields each corresponding to a cache lines in the cache, and certain bit fields in the repair mask array are initially set to indicate that a group of corresponding cache lines are defective. Thereafter the repair mask is updated by setting additional bit fields in the repair mask array to indicate that an additional group of corresponding cache lines are defective. Access to all defective cache lines is prevented based on the corresponding bit fields in the repair mask array. The initial setting of certain bit fields can take place at fabrication of the cache chip in response to testing of the cache lines. Additionally, the repair mask may be updated each time the computer system is booted in response to testing by the boot procedure. The repair mask may also be updated real-time during program execution in response to detection of an error associated with a particular cache line. Updating in real-time can be accomplished by counting a cumulative number of errors associated with a cache line, and then identifying the cache line as being defective only after a certain number of cumulative errors has occurred.
摘要翻译： 公开了一种动态地避免由计算机系统的处理器使用的高速缓存中的有缺陷的高速缓存行的方法。 使用具有每个对应于高速缓存中的高速缓存行的位字段阵列的修复掩码，并且初始设置修复掩码阵列中的某些位字段以指示一组对应的高速缓存行有缺陷。 此后，通过在修复掩码阵列中设置附加位字段来指示修复掩码被更新以指示附加的一组对应的高速缓存行是有缺陷的。 基于修复掩码阵列中的相应位字段来防止对所有有缺陷的高速缓存行的访问。 响应于高速缓存行的测试，可以在制造高速缓存芯片时进行某些位字段的初始设置。 此外，每当计算机系统引导时响应于引导过程的测试，可以更新修复掩码。 响应于检测到与特定高速缓存行相关联的错误，修复掩码也可以在程序执行期间被实时更新。 可以通过计数与高速缓存行相关联的错误的累积数量，然后将高速缓存行识别为在发生一定数量的累积错误之后的缺陷来实现。
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3.发明授权Dual cache directories with respective queue independently executing its content and allowing staggered write operations 失效具有相应队列的双缓存目录独立地执行其内容并允许交错的写入操作
公开(公告)号：US6085288A
公开(公告)日：2000-07-04
申请号：US839556
申请日：1997-04-14
CPC分类号： G06F12/0831
摘要： A method of storing values in a cache used by a processor of a computer system, the cache having two or more cache directories. An address tag associated with the memory block is written into a first cache directory during an initial processor cycle, the address tag is written into a second cache directory during the next or subsequent processor cycle. Another address tag associated with a different memory block may be read from the second cache directory during the initial processor cycle. Additionally, another address tag associated with yet a different memory block may be read from the first cache directory during the subsequent processor cycle. A write operation for the address tag may be placed into a write queue of the first cache directory, prior to writing the address tag into the first cache directory, and the same write operation may be placed into a write queue of the second cache directory, prior to said step of writing the address tag into the second cache directory; the write queue of the second cache directory executes its contents independently of the write queue of the first cache directory. This staggered writing ability imparts greater flexibility in carrying out write operations for a cache having multiple directories, thereby increasing performance.
摘要翻译： 一种在计算机系统的处理器使用的高速缓存中存储值的方法，所述高速缓存具有两个或多个高速缓存目录。 在初始处理器周期期间，与存储器块相关联的地址标签被写入第一高速缓存目录中，在下一个或后续处理器周期期间将地址标签写入第二高速缓存目录。 可以在初始处理器周期期间从第二高速缓存目录读取与不同存储器块相关联的另一地址标签。 此外，在随后的处理器周期期间，可以从第一高速缓存目录读取与另一个存储器块相关联的另一地址标签。 在将地址标签写入第一高速缓存目录之前，可以将地址标签的写入操作放入第一高速缓存目录的写入队列中，并且可以将相同的写入操作放入第二高速缓存目录的写入队列中， 在将所述地址标签写入所述第二高速缓存目录之前的所述步骤之前; 第二高速缓存目录的写入队列独立于第一高速缓存目录的写入队列来执行其内容。 这种交错的写入能力为对具有多个目录的高速缓存执行写入操作赋予更大的灵活性，从而提高性能。
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4.发明授权Dual associative-cache directories allowing simultaneous read operation using two buses with multiplexors, address tags, memory block control signals, single clock cycle operation and error correction 失效双重关联缓存目录允许使用两个总线同时读操作，多路复用器，地址标签，存储块控制信号，单时钟周期操作和纠错
公开(公告)号：US6023746A
公开(公告)日：2000-02-08
申请号：US839558
申请日：1997-04-14
CPC分类号： G11C29/76 , G06F12/0846
摘要： A method of accessing values stored in a cache used by a processor of a computer system, whereby two read operations may occur simultaneously is disclosed. Memory blocks from a memory device are loaded into respective cache lines of the cache, and address tags associated with the memory blocks are written into two redundant cache directories of the cache. Thereafter, a first memory block can be read from the cache using the first cache directory, while a second memory block is simultaneously read from the cache using the second cache directory. The cache can have a single cache entry array, or two (redundant) cache entry arrays connected respectively to the two cache directories. If an error occurs when examining a particular address tag in one cache directory, then a redundant address tag can be substituted for the particular address tag by examining a corresponding line of the other cache directory.
摘要翻译： 公开了存储在由计算机系统的处理器使用的高速缓存中的值的方法，由此可以同时发生两个读取操作。 来自存储器件的存储器块被加载到高速缓存的相应高速缓存行中，并且与存储块相关联的地址标签被写入高速缓存的两个冗余高速缓存目录中。 此后，可以使用第一高速缓存目录从高速缓存读取第一存储器块，同时使用第二高速缓存目录从高速缓存同时读取第二存储器块。 高速缓存可以具有单个高速缓存条目数组或两个（冗余）高速缓存条目数组，分别连接到两个高速缓存目录。 如果在检查一个缓存目录中的特定地址标签时发生错误，则可以通过检查另一个缓存目录的相应行来替代特定地址标签的冗余地址标签。
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公开(公告)号：US5958068A
公开(公告)日：1999-09-28
申请号：US839554
申请日：1997-04-14
CPC分类号： G06F12/126 , G06F12/0802 , G11C29/846 , G06F2212/1032
摘要： A method of bypassing defects in a cache used by a processor of a computer system. A repair mask has an array of bit fields corresponding to cache lines in the cache, and when a particular cache line in the cache is identified as being defective, a corresponding bit field in the repair mask array is set to indicate that the particular cache line is defective, and further access to the defective cache line is prevented, based on the corresponding bit field in the repair mask array. The repair mask can be used to prevent the defective cache line from ever resulting in a cache hit, and to prevent the defective cache line from ever being chosen as a victim for cache replacement. Using a set associative cache, the defective cache line is thereby effectively removed from its respective congruence class. This approach allows the cache to use all non-defective cache lines without any cache lines being reserved for redundancy.
摘要翻译： 绕过由计算机系统的处理器使用的高速缓存中的缺陷的方法。 修复掩模具有对应于高速缓存中的高速缓存行的位字段阵列，并且当高速缓存中的特定高速缓存行被识别为有缺陷时，修复掩码阵列中的相应位字段被设置为指示特定高速缓存行 基于修复掩码阵列中的相应位字段，防止对缺陷高速缓存线的进一步访问。 可以使用修复掩码来防止有缺陷的高速缓存线从不导致高速缓存命中，并防止有缺陷的高速缓存行被选为高速缓存替换的受害者。 使用集合关联高速缓存，从而有效地从有缺陷的高速缓存行中删除其相应的一致等级。 这种方法允许高速缓存使用所有无缺陷高速缓存行，而没有为冗余保留任何高速缓存行。
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6.发明授权Multiple cache directories for non-arbitration concurrent accessing of a cache memory 失效多个缓存目录，用于缓存内存的非仲裁并发访问
公开(公告)号：US5943686A
公开(公告)日：1999-08-24
申请号：US834492
申请日：1997-04-14
CPC分类号： G06F12/0831 , G06F12/0846
摘要： A method of accessing a cache used by a processor of a computer system, to eliminate arbitration logic which would otherwise be required to handle operations from multiple snooping devices. A plurality of cache directories are provided in the cache, respectively connected directly to a plurality of snooping devices using a plurality of interconnects. An operation from a given snooping device is then handled by using a respective cache directory to issue a response to a respective interconnect. For example, a first cache directory may be connected to a first interconnect on a processor side of the cache, and a second cache directory may be connected to a second interconnect on a system bus side of the cache. This construction allows handling of operations from multiple snooping devices without having to use critical path arbitration logic. Furthermore, this construction allows for improved cache access due to the physical placement of the multiple cache directories.
摘要翻译： 访问由计算机系统的处理器使用的高速缓存的方法，以消除否则将需要来处理来自多个窥探设备的操作的仲裁逻辑。 高速缓存中提供多个高速缓存目录，分别使用多个互连直接连接到多个窥探装置。 然后，通过使用相应的缓存目录来对相应的互连进行响应来处理来自给定窥探设备的操作。 例如，第一高速缓存目录可以连接到高速缓存的处理器侧上的第一互连，并且第二高速缓存目录可以连接到高速缓存的系统总线侧上的第二互连。 这种结构允许处理来自多个窥探设备的操作，而不必使用关键路径仲裁逻辑。 此外，这种结构允许由于多个高速缓存目录的物理放置而改进的高速缓存访问。
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公开(公告)号：US5883904A
公开(公告)日：1999-03-16
申请号：US834491
申请日：1997-04-14
CPC分类号： G06F11/1064
摘要： A method of correcting an erroneous bit field in a cache used by a processor is disclosed. A first array stores a plurality of bit fields, respectively connected to error checking circuits, and a substitute bit field is supplied for a bit field in the first array that is found to be erroneous by the error checking circuits, the substitute bit field being read from a second array which redundantly stores the bit fields. The error checking circuits can be connected to a parity error control unit which reads the substitute bit field from the second array. The parity error control unit forces the cache into a busy mode when any of the error checking circuits indicates that a bit field is erroneous, and maintains the busy mode until the substitute bit field is supplied. The error checking circuits can check the parity of a plurality of subsets of the bit fields in the first array and indicate which of the subsets are erroneous, and the parity error controller then reads only subsets of the bit fields in the second array corresponding to those subsets in the first array that are erroneous.
摘要翻译： 公开了一种校正由处理器使用的高速缓存中的错误位字段的方法。 第一阵列存储分别连接到错误检查电路的多个比特字段，并且为错误检查电路发现错误的第一阵列中的比特字段提供替代比特字段，替代比特字段被读取 从第二个阵列冗余存储位字段。 错误检查电路可以连接到从第二阵列读取替代位字段的奇偶校验错误控制单元。 当任何错误检查电路指示位字段是错误的时，奇偶校验错误控制单元强制高速缓存进入忙模式，并保持忙模式，直到提供替代位字段。 错误检查电路可以检查第一阵列中的位字段的多个子集的奇偶校验，并且指示哪些子集是错误的，并且奇偶校验错误控制器然后仅读取与那些相应的第二阵列中的第二阵列中的位字段的子集 第一个数组中的子集是错误的。
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公开(公告)号：US5867511A
公开(公告)日：1999-02-02
申请号：US834118
申请日：1997-04-14
CPC分类号： G11C29/88 , G06F11/1064 , G06F12/0802 , G06F12/126
摘要： A method of determining if a requested memory block of a memory device is contained in a cache used by a processor of a computer system is disclosed. An address associated with the requested memory block is compared to a plurality of address tags stored in a cache directory of the cache, while simultaneously performing error checks on the address tags. Corrected address tags are supplied for any erroneous address tags indicated by the error checks, and any corrected address tags are also compared to the address of the requested memory block. The error check may be a parity check of a portion of the address tag, either the entire portion, or of several subsets having a number of bits smaller than the address tag. The address tags can be stored in a redundant cache directory of the cache, and the corrected address tags supplied by substituting corresponding address tags from the redundant cache directory. By moving error checking out of the critical retrieval path of the cache, the present invention results in improved performance (increased speed).
摘要翻译： 公开了一种确定所请求的存储器件的存储块是否包含在计算机系统的处理器使用的高速缓存中的方法。 将与所请求的存储器块相关联的地址与存储在高速缓存的高速缓存目录中的多个地址标签进行比较，同时对地址标签执行错误检查。 对于由错误检查指示的任何错误的地址标签提供了更正的地址标签，并且还将任何校正的地址标签与请求的存储器块的地址进行比较。 错误检查可以是地址标签的一部分，即整个部分或具有小于地址标签的位数的几个子集的奇偶校验。 地址标签可以存储在高速缓存的冗余高速缓存目录中，并通过从冗余高速缓存目录中替换相应的地址标签来提供更正的地址标签。 通过移动从高速缓存的关键检索路径出来的错误检查，本发明导致改进的性能（提高速度）。
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公开(公告)号：US20090292963A1
公开(公告)日：2009-11-26
申请号：US12123540
申请日：2008-05-20
CPC分类号： G06F11/27 , G01R31/318307 , G01R31/3187
摘要： A method for testing an electronic circuit comprises selecting a first log interval, a first log start pattern, a first log end pattern, and a first subset range of LBIST patterns from a plurality of LBIST patterns arranged in an order, wherein each LBIST pattern of the subset range of LBIST patterns causes an associated output of an electronic circuit. The method tests an electronic circuit in a first test by applying to the electronic circuit the first subset range of LBIST patterns sequentially in the order, thereby generating a first plurality of associated outputs. The method stores a first subset of associated outputs based on the first log interval, the first log start pattern, and the first log end pattern. The method compares the subset of associated outputs with known outputs to identify a first output mismatch.
摘要翻译： 一种用于测试电子电路的方法包括从按顺序布置的多个LBIST图案中选择第一对数间隔，第一对数起始图案，第一日志结束图案和LBIST图案的第一子范围，其中每个LBIST图案 LBIST模式的子集范围导致电子电路的相关输出。 该方法在第一次测试中通过以顺序向电子电路应用LBIST图案的第一子范围，从而产生第一多个相关联的输出，来测试电子电路。 该方法基于第一日志间隔，第一日志开始模式和第一日志结束模式来存储关联输出的第一子集。 该方法将相关输出的子集与已知输出进行比较，以识别第一输出失配。
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10.发明授权Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor 失效用于间接访问内存映射资源的支持接口以减少带外支持处理器的系统连接的方法公开(公告)号：US07418541B2
公开(公告)日：2008-08-26
申请号：US11055404
申请日：2005-02-10
申请人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
发明人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
CPC分类号： G06F15/7842
摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.
摘要翻译： 提供了一种用于存储器映射资源的支持接口的方法和装置。 支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。 内存映射支持接口更新内存，内存映射寄存器或内存映射资源。 该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。 结构命令转换为FSI协议，并转发到附加的支持芯片以访问存储器映射的资源，并且来自支持芯片的响应被转换回到结构响应分组。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。 织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。 系统还报告遇到的任何错误。
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