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58 条记录 (耗时 0.035 秒)

    System for stressing a memory integrated circuit die
    1.
    发明授权
    System for stressing a memory integrated circuit die 失效
    用于强调存储器集成电路管芯的系统

    公开(公告)号：US5898629A

    公开(公告)日：1999-04-27

    申请号：US915757

    申请日：1997-08-21

    申请人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

    发明人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

    IPC分类号： G11C29/50 ,  G11C29/56 ,  G11C7/00

    CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C29/56

    摘要： A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.

    摘要翻译： 能够在晶片烧录期间使用的存储器自应力模式，例如用于动态随机存取存储器（DRAM）集成电路。 将老化的电源电压和接地电压传送到多个存储单元存储电容器的公共节点以及耦合到位线的均衡节点。 全行高测试在二进制低逻辑电平和二进制高逻辑电平之间循环字线，从而通过施加不同极性的应力电压来强调存储器单元存储电容器的电介质。 半行高测试周期交替字线序列的字线，从而强调相邻字线之间的不期望的短路连接。

    Method of stress testing memory integrated circuits
    2.
    发明授权
    Method of stress testing memory integrated circuits 失效
    记忆体集成电路应力测试方法

    公开(公告)号：US5852581A

    公开(公告)日：1998-12-22

    申请号：US663515

    申请日：1996-06-13

    申请人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

    发明人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

    IPC分类号： G11C29/50 ,  G11C29/56 ,  G11C7/00

    CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C29/56

    摘要： A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.

    摘要翻译： 能够在晶片烧录期间使用的存储器自应力模式，例如用于动态随机存取存储器（DRAM）集成电路。 将老化的电源电压和接地电压传送到多个存储单元存储电容器的公共节点以及耦合到位线的均衡节点。 全行高测试在二进制低逻辑电平和二进制高逻辑电平之间循环字线，从而通过施加不同极性的应力电压来强调存储器单元存储电容器的电介质。 半行高测试周期交替字线序列的字线，从而强调相邻字线之间的不期望的短路连接。

    Wafer level burn-in of memory integrated circuits
    3.
    发明授权
    Wafer level burn-in of memory integrated circuits 有权
    晶圆级老化内存集成电路

    公开(公告)号：US06233185B1

    公开(公告)日：2001-05-15

    申请号：US09257403

    申请日：1999-02-25

    申请人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

    发明人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

    IPC分类号： G11C1300

    CPC分类号： G11C29/006 ,  G11C11/401 ,  G11C29/50 ,  G11C2029/1202

    摘要： A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.

    摘要翻译： 能够在晶片烧录期间使用的存储器自应力模式，例如用于动态随机存取存储器（DRAM）集成电路。 将老化的电源电压和接地电压传送到多个存储单元存储电容器的公共节点以及耦合到位线的均衡节点。 全行高测试在二进制低逻辑电平和二进制高逻辑电平之间循环字线，从而通过施加不同极性的应力电压来强调存储器单元存储电容器的电介质。 半行高测试周期交替字线序列的字线，从而强调相邻字线之间的不期望的短路连接。

    Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer
    4.
    发明授权
    Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer 失效
    用于从半导体晶片上的其它IC隔离短路集成电路（IC）的方法

    公开(公告)号：US07567091B2

    公开(公告)日：2009-07-28

    申请号：US12017262

    申请日：2008-01-21

    申请人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    发明人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    IPC分类号： G01R31/26

    CPC分类号： G01R31/025 ,  G01R31/2884

    摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

    摘要翻译： 用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路 电路。 控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。 短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。 结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。

    Device and method for isolating a short-circuited integrated circuit (IC) from other IC's on a semiconductor wafer
    5.
    发明授权
    Device and method for isolating a short-circuited integrated circuit (IC) from other IC's on a semiconductor wafer 失效
    用于从半导体晶片上的其他IC隔离短路集成电路（IC）的装置和方法

    公开(公告)号：US06313658B1

    公开(公告)日：2001-11-06

    申请号：US09083819

    申请日：1998-05-22

    申请人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    发明人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    IPC分类号： G01R3126

    CPC分类号： G01R31/025 ,  G01R31/2884

    摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

    摘要翻译： 用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路 电路。 控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。 短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。 结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。

    Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer
    7.
    发明授权
    Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer 失效
    用于从半导体晶片上的其它IC隔离短路集成电路（IC）的方法

    公开(公告)号：US07276926B2

    公开(公告)日：2007-10-02

    申请号：US11607267

    申请日：2006-12-01

    申请人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    发明人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    IPC分类号： G01R31/26

    CPC分类号： G01R31/025 ,  G01R31/2884

    摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

    摘要翻译： 用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路 电路。 控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。 短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。 结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。

    Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer
    9.
    发明授权
    Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer 失效
    用于从半导体晶片上的其它IC隔离短路集成电路（IC）的装置和方法

    公开(公告)号：US06831475B2

    公开(公告)日：2004-12-14

    申请号：US10690496

    申请日：2003-10-21

    申请人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    发明人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    IPC分类号： G01R3126

    CPC分类号： G01R31/025 ,  G01R31/2884

    摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

    摘要翻译： 用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路 电路。 控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。 短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。 结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。