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    Method for sorting integrated circuit devices
    2.
    发明授权
    Method for sorting integrated circuit devices 失效
    集成电路器件分类方法

    公开(公告)号：US07682847B2

    公开(公告)日：2010-03-23

    申请号：US12248368

    申请日：2008-10-09

    申请人： Raymond J. Beffa

    发明人： Raymond J. Beffa

    IPC分类号： H01L21/20

    CPC分类号： B07C5/3412 ,  B07C5/344 ,  G01R31/2851 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.

    摘要翻译： 一种用于分类具有基本上唯一的识别（ID）代码（诸如熔丝ID）的集成电路（IC）装置的方法，其包括自动读取每个IC器件的ID码并根据它们对IC器件进行分类 自动读取ID码，被披露。

    Sorting a group of integrated circuit devices for those devices requiring special testing
    3.
    发明授权
    Sorting a group of integrated circuit devices for those devices requiring special testing 失效
    对需要特殊测试的那些设备对一组集成电路设备进行排序

    公开(公告)号：US07502659B2

    公开(公告)日：2009-03-10

    申请号：US11543246

    申请日：2006-10-03

    申请人： Raymond J. Beffa

    发明人： Raymond J. Beffa

    IPC分类号： G06F19/00

    CPC分类号： G01R31/2894 ,  G01R31/31718 ,  G01R31/319 ,  G06F11/006 ,  H01L21/67271 ,  H01L22/14 ,  H01L22/20 ,  H01L2223/5444

    摘要： A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and those requiring standard testing includes storing fabrication deviation data, probe data, and test data in association with the fuse ID of each of the devices indicating each of the devices requires either enhanced reliability testing or standard testing. The fuse ID of each of the devices is then automatically read before, during, or after standard testing of the devices. The testing process requirement data stored in association with the fuse ID of each of the devices is then accessed, and the devices are sorted in accordance with the accessed data into those devices requiring enhanced reliability testing and those requiring standard testing.

    摘要翻译： 将具有熔丝识别（ID）的类型的集成电路（IC）装置分类到需要增强的可靠性测试的那些装置和需要进行标准测试的装置的方法包括存储制造偏差数据，探针数据和与熔丝ID相关联的测试数据 指示每个设备的每个设备需要增强的可靠性测试或标准测试。 然后在设备的标准测试之前，期间或之后自动读取每个设备的熔丝ID。 然后访问与每个设备的熔丝ID相关联地存储的测试过程要求数据，并且根据所访问的数据将设备分类到需要增强的可靠性测试的设备和需要标准测试的那些设备中。

    256 Meg dynamic random access memory
    5.
    发明授权
    256 Meg dynamic random access memory 失效

    公开(公告)号：US07477556B2

    公开(公告)日：2009-01-13

    申请号：US09899977

    申请日：2001-07-06

    申请人： Brent Keeth ,  Layne G. Bunker ,  Raymond J. Beffa ,  Frank F. Ross

    发明人： Brent Keeth ,  Layne G. Bunker ,  Raymond J. Beffa ,  Frank F. Ross

    IPC分类号： G11C11/00

    CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C5/145 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/46 ,  G11C29/787 ,  G11C2029/0407 ,  H01L27/10805 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

    摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

    Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer
    8.
    发明授权
    Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer 失效
    用于从半导体晶片上的其它IC隔离短路集成电路（IC）的方法

    公开(公告)号：US07276926B2

    公开(公告)日：2007-10-02

    申请号：US11607267

    申请日：2006-12-01

    申请人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    发明人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    IPC分类号： G01R31/26

    CPC分类号： G01R31/025 ,  G01R31/2884

    摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

    摘要翻译： 用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路 电路。 控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。 短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。 结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。

    Sorting a group of integrated circuit devices for those devices requiring special testing
    9.
    发明授权
    Sorting a group of integrated circuit devices for those devices requiring special testing 有权

    公开(公告)号：US07107117B2

    公开(公告)日：2006-09-12

    申请号：US10791193

    申请日：2004-03-02

    申请人： Raymond J. Beffa

    发明人： Raymond J. Beffa

    IPC分类号： G06F19/00

    CPC分类号： G01R31/2894 ,  G01R31/31718 ,  G01R31/319 ,  G06F11/006 ,  H01L21/67271 ,  H01L22/14 ,  H01L22/20 ,  H01L2223/5444

    摘要： A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and those requiring standard testing includes storing fabrication deviation data, probe data, and test data in association with the fuse ID of each of the devices indicating each of the devices requires either enhanced reliability testing or standard testing. The fuse ID of each of the devices is then automatically read before, during, or after standard testing of the devices. The testing process requirement data stored in association with the fuse ID of each of the devices is then accessed, and the devices are sorted in accordance with the accessed data into those devices requiring enhanced reliability testing and those requiring standard testing.