公开(公告)号：US07567091B2

公开(公告)日：2009-07-28

申请号：US12017262

申请日：2008-01-21

申请人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

发明人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

IPC分类号： G01R31/26

CPC分类号： G01R31/025 ,  G01R31/2884

摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

摘要翻译： 用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路 电路。 控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。 短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。 结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。

公开(公告)号：US06621759B1

公开(公告)日：2003-09-16

申请号：US10162937

申请日：2002-06-06

申请人： William K. Waller

发明人： William K. Waller

IPC分类号： G11C800

CPC分类号： G11C8/10 ,  G11C8/08

摘要： A wordline decoder circuit for a semiconductor memory device is disclosed, providing a new combination of optimized speed, power, and device area with self-latching wordline output and prevention of process parasitic latch-up. A method for high-speed copying of data from row to row within a memory section is disclosed for reducing time required to stress and to test the device. The wordline decoder circuit as disclosed can implement the row-copy method as disclosed.

摘要翻译： 公开了一种用于半导体存储器件的字线解码器电路，其提供了优化的速度，功率和器件面积与自锁定字线输出和防止过程寄生闭锁的新组合。 公开了一种用于在存储器部分内从行到行高速复制数据的方法，用于减少压力和测试器件所需的时间。 如所公开的字线解码器电路可以实现所公开的行复制方法。

公开(公告)号：US06430094B1

公开(公告)日：2002-08-06

申请号：US09571206

申请日：2000-05-16

申请人： William K. Waller

发明人： William K. Waller

IPC分类号： G11C700

CPC分类号： G11C29/80 ,  G11C29/12 ,  G11C29/83

摘要： A memory device having two or more memory arrays and a testpath operatively connected to one of the memory arrays and not operatively connected to another of the memory arrays at substantially the same time. The memory device may include multiplexers and sense amplifiers to connect the datapath to the memory arrays. The memory device may also include a datapath connected to two or more memory arrays at the same time through multiplexers and sense amplifiers. The memory array may also be embodied as a memory system, including a processor, control logic, and the memory device. A method of operating a testpath of the memory device includes generating control signals to operatively connect the testpath to one of the memory arrays, and not to connect the testpath to another of the memory arrays at substantially the same time.

摘要翻译： 具有两个或多个存储器阵列的存储器件和可操作地连接到存储器阵列中的一个的测试路径，并且基本上同时不可操作地连接到另一个存储器阵列。 存储器件可以包括将数据路径连接到存储器阵列的多路复用器和读出放大器。 存储器件还可以包括通过多路复用器和读出放大器同时连接到两个或更多个存储器阵列的数据通路。 存储器阵列还可以被实现为包括处理器，控制逻辑和存储器件的存储器系统。 操作存储器件的测试路径的方法包括产生控制信号以将测试路径可操作地连接到存储器阵列之一，而不是在基本相同的时间将测试路径连接到另一个存储器阵列。

公开(公告)号：US06313658B1

公开(公告)日：2001-11-06

申请号：US09083819

申请日：1998-05-22

申请人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

发明人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

IPC分类号： G01R3126

CPC分类号： G01R31/025 ,  G01R31/2884

摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

摘要翻译： 用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路 电路。 控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。 短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。 结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。

公开(公告)号：US6134160A

公开(公告)日：2000-10-17

申请号：US406385

申请日：1999-09-27

申请人： William K. Waller ,  Kuo-Yuan Hsu

发明人： William K. Waller ,  Kuo-Yuan Hsu

IPC分类号： G11C7/10 ,  G11C7/18 ,  G11C29/00

CPC分类号： G11C29/808 ,  G11C29/81 ,  G11C7/1006 ,  G11C7/18 ,  G11C29/846 ,  G11C29/848

摘要： An architecture for a high-capacity high-speed semiconductor memory device is disclosed. The semiconductor memory device includes memory cell arrays (406) having local word lines and bit lines. The memory cell arrays (406) are further arranged into array groups (402a-402d and 404a-404d). The local word lines (410a-410d) of the memory cell arrays of the same group are commonly connected to global word lines (408). The array groups (402a-402d and 404a-404d) provide data access paths to their respective memory cells by sets of input/output (I/O) lines (416a-416d and 420a-420d). The I/O line sets (416a-416d and 420a-420d) are coupled to data amplifiers by interarray multiplexers (MUXs) (422a-422d). The interarray MUXs (422a-422d) enable defective global word lines of one array group to be replaced by redundant global word lines of an adjacent array group.

摘要翻译： 公开了一种用于大容量高速半导体存储器件的架构。 半导体存储器件包括具有本地字线和位线的存储单元阵列（406）。 存储单元阵列（406）还被布置成阵列组（402a-402d和404a-404d）。 同一组的存储单元阵列的本地字线（410a-410d）通常连接到全局字线（408）。 阵列组（402a-402d和404a-404d）通过一组输入/输出（I / O）线（416a-416d和420a-420d）提供到它们各自存储单元的数据访问路径。 I / O线组（416a-416d和420a-420d）通过阵列间复用器（MUX）（422a-422d）耦合到数据放大器。 串联MUX（422a-422d）使一个阵列组的缺陷全局字线能够被相邻阵列组的冗余全局字线代替。

公开(公告)号：US5930184A

公开(公告)日：1999-07-27

申请号：US878752

申请日：1997-06-19

申请人： William K. Waller

发明人： William K. Waller

IPC分类号： G11C29/00 ,  G11C29/12 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C29/12 ,  G11C29/83

摘要： A memory device having two or more memory arrays and a testpath operatively connected to one of the memory arrays and not operatively connected to another of the memory arrays at substantially the same time. The memory device may include multiplexers and sense amplifiers to connect the datapath to the memory arrays. The memory device may also include a datapath connected to two or more memory arrays at the same time through multiplexers and sense amplifiers. The memory array may also be embodied as a memory system, including a processor, control logic, and the memory device. A method of operating a testpath of the memory device includes generating control signals to operatively connect the testpath to one of the memory arrays, and not to connect the testpath to another of the memory arrays at substantially the same time.

摘要翻译： 具有两个或多个存储器阵列的存储器件和可操作地连接到存储器阵列中的一个的测试路径，并且基本上同时不可操作地连接到另一个存储器阵列。 存储器件可以包括将数据路径连接到存储器阵列的多路复用器和读出放大器。 存储器件还可以包括通过多路复用器和读出放大器同时连接到两个或更多个存储器阵列的数据通路。 存储器阵列还可以被实现为包括处理器，控制逻辑和存储器件的存储器系统。 操作存储器件的测试路径的方法包括产生控制信号以将测试路径可操作地连接到存储器阵列之一，而不是在基本相同的时间将测试路径连接到另一个存储器阵列。

公开(公告)号：US5787311A

公开(公告)日：1998-07-28

申请号：US528181

申请日：1995-09-14

申请人： William K. Waller

发明人： William K. Waller

IPC分类号： G11C11/401 ,  G09G5/14 ,  G09G5/39 ,  G11C7/10 ,  G06F13/00

CPC分类号： G09G5/14 ,  G09G5/39 ,  G11C7/1072 ,  G09G2360/126

摘要： An integrated circuit (IC) architecture includes a bit mask register (BMR) and a serial access memory (SAM) which share address decode and clock circuitry within a multiport random access memory chip. The integrated circuit also includes a random access memory and circuitry for performing a bit masked transfer between the serial access memory and the random access memory. Mask data may be clocked into the bit mask register, which may be cleared upon completion of a data transfer between the random access memory and the serial access memory. The mask data may also be inverted upon being transferred between the random access memory and the bit mask register. This architecture provides CLEAR and TRUE or COMPLEMENT masked transfer output ability in the BMR, and has utility in real-time video windowing in memory mapped computer graphics.

摘要翻译： 集成电路（IC）架构包括在多端口随机存取存储器芯片中共享地址解码和时钟电路的位掩码寄存器（BMR）和串行访问存储器（SAM）。 集成电路还包括随机存取存储器和用于在串行访问存储器和随机存取存储器之间执行位屏蔽转移的电路。 掩码数据可以被计时到位掩码寄存器中，这可以在随机访问存储器和串行访问存储器之间的数据传送完成时被清除。 当在随机存取存储器和位掩码寄存器之间传送时，掩码数据也可以被反转。 该架构在BMR中提供CLEAR和TRUE或COMPLEMENT屏蔽传输输出能力，并且可用于内存映射计算机图形中的实时视频窗口。

公开(公告)号：US5555429A

公开(公告)日：1996-09-10

申请号：US437447

申请日：1995-05-08

申请人： Ward D. Parkinson ,  William K. Waller ,  Mirmajid Seyyedy

发明人： Ward D. Parkinson ,  William K. Waller ,  Mirmajid Seyyedy

IPC分类号： G06F15/78 ,  G06F15/80 ,  G06F15/16

CPC分类号： G06F15/8015 ,  G06F15/7821 ,  G06F15/7896

摘要： Presented is an integrated circuit chip including a random access memory (RAM) array, serial access memory (SAM), an arithmetic logic unit, a bidirectional shift register, and masking circuitry. The arithmetic logic unit, SAM, shift register, and masking circuitry are all as wide as one side of the RAM array, and are all communicable with each other via data transfer means. This allows wide word processing, user configurable for parallel processing. Bits masked by the masking circuitry are selectable by data in the bidirectional shift register, providing shiftable masking means. Random access and serial access are done through separate ports. The bidirectional shift register is optionally serially accessible. Methods of use are also presented.

公开(公告)号：US5488583A

公开(公告)日：1996-01-30

申请号：US311582

申请日：1994-09-22

申请人： Adrian E. Ong ,  William K. Waller ,  Paul S. Zagar

发明人： Adrian E. Ong ,  William K. Waller ,  Paul S. Zagar

IPC分类号： G11C7/10 ,  G11C7/18 ,  G11C29/36 ,  G11C7/00 ,  G11C29/00

CPC分类号： G11C29/36 ,  G11C7/1006 ,  G11C7/18

摘要： A memory integrated circuit chip of a predefined circuit topology has an on-chip topology logic driver. The topology logic driver selectively inverts data being written to and read from addressed memory cells in the memory IC based upon location of the addressed memory cells in the circuit topology of the memory array. The topology logic driver is preferably a logic circuit that embodies a boolean function defining the circuit topology. A method for testing and producing such memory ICs is also described.

摘要翻译： 预定义电路拓扑的存储器集成电路芯片具有片上拓扑逻辑驱动器。 拓扑逻辑驱动器基于存储器阵列的电路拓扑中寻址的存储器单元的位置选择性地反转正在写入存储器IC中的寻址存储器单元的数据和从其读出的数据。 拓扑逻辑驱动器优选地是实现定义电路拓扑的布尔函数的逻辑电路。 还描述了用于测试和产生这种存储器IC的方法。

公开(公告)号：US5313433A

公开(公告)日：1994-05-17

申请号：US943970

申请日：1992-09-11

申请人： William K. Waller

发明人： William K. Waller

IPC分类号： G11C8/04 ,  G11C8/10 ,  G11C8/00

CPC分类号： G11C8/04 ,  G11C8/10

摘要： The invention is the circuit and method for selecting a window of desired address locations to be written. A start address and a stop address activate a start and stop decoder output respectively. The active start and stop decoder output signals are rippled through start and stop ripple circuitry which enables the outputs electrically interposed between the start and stop addresses respectively. AND circuitry ensures that only the outputs interposed between the start and stop addresses are activated in addition to the start and stop decoder outputs. The activated outputs comprise the window of desired address locations to be written.

摘要翻译： 本发明是用于选择要写入的所需地址位置的窗口的电路和方法。 起始地址和停止地址分别激活启动和停止解码器输出。 激活的启动和停止解码器输出信号通过启动和停止纹波电路波纹，使得输出分别电连接在起始地址和停止地址之间。 AND电路确保除了启动和停止解码器输出之外，仅激活插入在起始地址和停止地址之间的输出。 激活的输出包括要写入的所需地址位置的窗口。