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Patent Agency Ranking
公开(公告)号：US10158156B2
公开(公告)日：2018-12-18
申请号：US15187219
申请日：2016-06-20
Applicant: Raytheon Company
Inventor： Christopher M. Laighton , Edward A. Watters , Keith R. Kessler
Abstract: A microwave transmission line having a coplanar waveguide and a pair of conductive members, each one of the pair of conductive members having a proximal end disposed on a portion of a corresponding one of a pair of ground plane conductors of the coplanar waveguide and a distal end disposed over, and vertically spaced from, a region between a center conductor of the coplanar waveguide and a corresponding one of the pair of ground plane conductors of the coplanar waveguide. The distal ends are laterally separated from each other by a region disposed over the center conductor.
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公开(公告)号：US20190097580A1
公开(公告)日：2019-03-28
申请号：US15718504
申请日：2017-09-28
Applicant: Raytheon Company
Inventor： Christopher M. Laighton , Alan J. Bielunis , Edward A. Watters
Abstract: An amplifier having a Radio Frequency (RF) power level detector circuit for producing a control signal in accordance with a power level of an RF input signal. The control signal indicates whether the power level of the input signal is within a predetermined range of power levels greater than zero. A bias circuit is fed by the control signal, for producing a fixed bias voltage at a gate electrode of a field effect transistor (FET) to establish a predetermined quiescent current for the FET when the control signal indicates the power level of the RF input signal is within the predetermined range of power levels and to reduce the bias voltage to reduce the predetermined quiescent current when the control signal indicates the power level of the RF input signal is below the predetermined range of power levels.
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公开(公告)号：US10263566B1
公开(公告)日：2019-04-16
申请号：US15718504
申请日：2017-09-28
Applicant: Raytheon Company
Inventor： Christopher M. Laighton , Alan J. Bielunis , Edward A. Watters
Abstract: An amplifier having a Radio Frequency (RF) power level detector circuit for producing a control signal in accordance with a power level of an RF input signal. The control signal indicates whether the power level of the input signal is within a predetermined range of power levels greater than zero. A bias circuit is fed by the control signal, for producing a fixed bias voltage at a gate electrode of a field effect transistor (FET) to establish a predetermined quiescent current for the FET when the control signal indicates the power level of the RF input signal is within the predetermined range of power levels and to reduce the bias voltage to reduce the predetermined quiescent current when the control signal indicates the power level of the RF input signal is below the predetermined range of power levels.
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公开(公告)号：US20180131066A1
公开(公告)日：2018-05-10
申请号：US15187219
申请日：2016-06-20
Applicant: Raytheon Company
Inventor： Christopher M. Laighton , Edward A. Watters , Keith R. Kessler
IPC: H01P3/00
CPC classification number: H01P3/003 , H01P3/006 , H01P11/003 , H05K1/0219 , H05K2201/0715
Abstract: A microwave transmission line having a coplanar waveguide and a pair of conductive members, each one of the pair of conductive members having a proximal end disposed on a portion of a corresponding one of a pair of ground plane conductors of the coplanar waveguide and a distal end disposed over, and vertically spaced from, a region between a center conductor of the coplanar waveguide and a corresponding one of the pair of ground plane conductors of the coplanar waveguide. The distal ends are laterally separated from each other by a region disposed over the center conductor.
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公开(公告)号：US09634613B1
公开(公告)日：2017-04-25
申请号：US15073853
申请日：2016-03-18
Applicant: Raytheon Company
Inventor： Edward A. Watters , Christopher M. Laighton , John P. Bettencourt
CPC classification number: H03F1/0233 , H03F1/0205 , H03F1/301 , H03F3/193 , H03F3/505 , H03F2200/18 , H03F2200/219 , H03F2200/282 , H03F2200/291 , H03F2200/42 , H03F2200/451 , H03F2200/75
Abstract: A depletion mode FET having a source electrode connected to ground; and a bias circuit for producing a bias current for a gate electrode of the FET. The bias circuit includes a pair of source follower transistors circuits; a first one of the pair of two source follower transistor circuits being coupled between a first voltage supply having a first polarity relative to the ground potential and a second voltage supply having a second polarity relative to ground potential, the first polarity being opposite to the second polarity, the first one of the pair of the source follower transistor circuits supplying a control signal to a second one of the pair of source follower transistor circuits. The second one of the pair of source follower transistors circuits is coupled between the second voltage supply and the ground potential and wherein the second one of the pair of source follower transistor circuits produces a bias signal for the control electrode of the output transistor.
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