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公开(公告)号：US20110103128A1
公开(公告)日：2011-05-05
申请号：US12882685
申请日：2010-09-15
CPC分类号： G11C7/02 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0097 , G11C2213/31 , G11C2213/71 , G11C2213/72
摘要： Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.
摘要翻译： 一个实施例的非易失性半导体存储器件包括：存储单元阵列，包括彼此相交的多个第一和第二线，以及设置在第一和第二线的交点处的多个存储单元，并且在施加相同的电压时写入和擦除数据 极性; 以及写入电路，被配置为选择第一和第二行，并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。 在擦除操作中，写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间，将复位脉冲重复地提供给所选择的存储单元，直到数据被擦除。 复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。
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2.发明授权Nonvolatile semiconductor memory device in which polarities of voltages in forming operation and set operation are different from each other 有权非易失性半导体存储器件，其中成形操作和设定操作中的电压的极性彼此不同公开(公告)号：US08988925B2
公开(公告)日：2015-03-24
申请号：US13597318
申请日：2012-08-29
申请人： Reika Ichihara , Takayuki Tsukamoto
发明人： Reika Ichihara , Takayuki Tsukamoto
CPC分类号： G11C11/00 , G11C2013/0083
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.
摘要翻译： 根据实施例的非易失性半导体存储器件包括多个第一，第二线，多个存储单元和控制电路。 多个第二线延伸以与第一线相交。 多个存储单元设置在第一和第二线的交点处，并且每个都包括可变电阻器。 控制电路被配置为控制施加到存储器单元的电压。 控制电路在成形操作期间向可变电阻器施加第一脉冲电压。 此外，控制电路在设定操作期间向可变电阻施加第二脉冲电压，第二脉冲电压具有与第一脉冲电压相反的极性。 此外，控制电路在复位操作期间向可变电阻器施加第三脉冲电压，第三脉冲电压具有与第一脉冲电压相同的极性。
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公开(公告)号：US08324606B2
公开(公告)日：2012-12-04
申请号：US12563470
申请日：2009-09-21
IPC分类号： H01L47/00
CPC分类号： G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2481
摘要： A resistance change type memory of an aspect of the present invention including a first wiring configured to extend in a first direction, a second wiring configured to extend in a second direction crossing the first direction, a series circuit configured to connect to the first and second wirings, the series circuit including a non-ohmic element being more conductive in the first to second wiring direction than in the second to first direction and a resistance change type storage element in which data is stored according to a change of a resistance state, an energy supplying circuit configured to connect to the first wiring to supply energy to the first wiring, the energy being used to store the data in the resistance change type storage element, and a capacitance circuit configured to include a capacitive element and being connected to the second wiring.
摘要翻译： 本发明的一个方面的电阻变化型存储器包括：构造成沿第一方向延伸的第一布线，沿与第一方向交叉的第二方向延伸的第二布线;串联电路，被配置为连接到第一和第二端 布线，包括在第一至第二布线方向上比在第二至第一方向上更加导电的非欧姆元件的串联电路和根据电阻状态的变化存储数据的电阻变化型存储元件， 能量供给电路，被配置为连接到所述第一布线以向所述第一布线供应能量，所述能量用于将所述数据存储在所述电阻变化型存储元件中;以及电容电路，被配置为包括电容元件并连接到所述第二布线 接线。
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公开(公告)号：US08320158B2
公开(公告)日：2012-11-27
申请号：US12882685
申请日：2010-09-15
IPC分类号： G11C11/00
CPC分类号： G11C7/02 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0097 , G11C2213/31 , G11C2213/71 , G11C2213/72
摘要： Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.
摘要翻译： 一个实施例的非易失性半导体存储器件包括：存储单元阵列，包括彼此相交的多个第一和第二线，以及设置在第一和第二线的交点处的多个存储单元，并且在施加相同的电压时写入和擦除数据 极性; 以及写入电路，被配置为选择第一和第二行，并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。 在擦除操作中，写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间，将复位脉冲重复地提供给所选择的存储单元，直到数据被擦除。 复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。
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公开(公告)号：US20100237314A1
公开(公告)日：2010-09-23
申请号：US12563470
申请日：2009-09-21
CPC分类号： G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2481
摘要： A resistance change type memory of an aspect of the present invention including a first wiring configured to extend in a first direction, a second wiring configured to extend in a second direction crossing the first direction, a series circuit configured to connect to the first and second wirings, the series circuit including a non-ohmic element being more conductive in the first to second wiring direction than in the second to first direction and a resistance change type storage element in which data is stored according to a change of a resistance state, an energy supplying circuit configured to connect to the first wiring to supply energy to the first wiring, the energy being used to store the data in the resistance change type storage element, and a capacitance circuit configured to include a capacitive element and being connected to the second wiring.
摘要翻译： 本发明的一个方面的电阻变化型存储器包括：构造成沿第一方向延伸的第一布线，沿与第一方向交叉的第二方向延伸的第二布线;串联电路，被配置为连接到第一和第二端 布线，包括在第一至第二布线方向上比在第二至第一方向上更加导电的非欧姆元件的串联电路和根据电阻状态的变化存储数据的电阻变化型存储元件， 能量供给电路，被配置为连接到所述第一布线以向所述第一布线供应能量，所述能量用于将所述数据存储在所述电阻变化型存储元件中;以及电容电路，被配置为包括电容元件并连接到所述第二布线 接线。
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公开(公告)号：US08274815B2
公开(公告)日：2012-09-25
申请号：US12886931
申请日：2010-09-21
申请人： Reika Ichihara , Takayuki Tsukamoto
发明人： Reika Ichihara , Takayuki Tsukamoto
IPC分类号： G11C11/00
CPC分类号： G11C11/00 , G11C2013/0083
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.
摘要翻译： 根据实施例的非易失性半导体存储器件包括多个第一，第二线，多个存储单元和控制电路。 多个第二线延伸以与第一线相交。 多个存储单元设置在第一和第二线的交点处，并且每个都包括可变电阻器。 控制电路被配置为控制施加到存储器单元的电压。 控制电路在成形操作期间向可变电阻器施加第一脉冲电压。 此外，控制电路在设定操作期间向可变电阻施加第二脉冲电压，第二脉冲电压具有与第一脉冲电压相反的极性。 此外，控制电路在复位操作期间向可变电阻器施加第三脉冲电压，第三脉冲电压具有与第一脉冲电压相同的极性。
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7.发明申请NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA WRITE/DATA ERASE THEREIN 有权非易失性半导体存储器件及数据写入/数据擦除方法公开(公告)号：US20110026299A1
公开(公告)日：2011-02-03
申请号：US12713667
申请日：2010-02-26
CPC分类号： G11C5/025 , G11C13/0007 , G11C13/003 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76
摘要： A nonvolatile semiconductor memory device comprises: a plurality of first lines; a plurality of second lines; a plurality of memory cells each disposed at each of crossing-points of the first lines and the second lines and each comprising a variable resistor and a bi-directional diode; and a voltage control circuit configured to control a voltage of selected one of the first lines, unselected ones of the first lines, selected one of the second lines, and unselected ones of the second lines, respectively. The variable resistor is configured to change its resistance value depending on a polarity of a voltage applied thereto. The voltage control circuit is configured to apply a voltage pulse to the selected one of the first lines and to connect a capacitor of a certain capacitance to one end of the selected one of the second lines.
摘要翻译： 非易失性半导体存储器件包括：多条第一线; 多条第二线; 多个存储单元，每个存储单元分别设置在第一线和第二线的交叉点的每一个处，并且每个存储单元包括可变电阻器和双向二极管; 以及电压控制电路，被配置为分别控制所选择的第一行，未选择的第一行，所选择的第二行和未选择的第二行中的一个的电压。 可变电阻器被配置为根据施加到其的电压的极性来改变其电阻值。 电压控制电路被配置为向所选择的第一线中的一个施加电压脉冲，并且将一定电容的电容器连接到所选择的一条第二线路的一端。
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8.发明授权Non-volatile semiconductor memory device including memory cells with a variable resistor 有权包括具有可变电阻器的存储单元的非易失性半导体存储器件公开(公告)号：US08391048B2
公开(公告)日：2013-03-05
申请号：US12846198
申请日：2010-07-29
IPC分类号： G11C11/00
CPC分类号： G11C13/0061 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C13/0097 , G11C2013/0092
摘要： A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.
摘要翻译： 根据本发明的实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元，并且每个由可变电阻器形成，其以非易失性方式存储电阻值作为数据。 根据本发明的实施例的一个方面的非易失性半导体存储器件还包括一个控制器，用于选择给定的一个存储单元，产生用于擦除数据的擦除脉冲，并将擦除脉冲提供给 选择的存储单元。 擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。
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公开(公告)号：US08320157B2
公开(公告)日：2012-11-27
申请号：US12876637
申请日：2010-09-07
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0097 , G11C2213/13 , G11C2213/34 , G11C2213/72
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of first wirings, a plurality of second wirings intersecting the plurality of first wirings, and a plurality of memory cells provided at the intersections of the plurality of first and second wirings and each including a non-ohmic element and a variable resistance element connected in series. The control circuit selects one of the plurality of memory cells, generates an erasing pulse for erasing data from the selected memory cell, and supplies the erasing pulse to the selected memory cell. The control circuit executes data erase by applying a voltage of the erasing pulse to the non-ohmic element in the reverse bias direction.
摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制电路。 存储单元阵列包括多个第一布线，与多条第一布线相交的多条第二布线，以及多个存储单元，设置在多个第一布线和第二布线的交点处，每个包括非欧姆元件和 串联连接的可变电阻元件。 控制电路选择多个存储单元中的一个，产生用于从所选存储单元擦除数据的擦除脉冲，并将擦除脉冲提供给所选存储单元。 控制电路通过在反向偏置方向上向非欧姆元件施加擦除脉冲的电压来执行数据擦除。
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公开(公告)号：US20120012807A1
公开(公告)日：2012-01-19
申请号：US13182095
申请日：2011-07-13
申请人： Takeshi YAMAGUCHI , Hirofumi Inoue , Reika Ichihara , Takayuki Tsukamoto , Takashi Shigeoka , Katsuyuki Sekine , Shinya Aoki
发明人： Takeshi YAMAGUCHI , Hirofumi Inoue , Reika Ichihara , Takayuki Tsukamoto , Takashi Shigeoka , Katsuyuki Sekine , Shinya Aoki
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , H01L27/2409 , H01L45/08 , H01L45/1233
摘要： A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.
摘要翻译： 实施例中的半导体存储器件包括存储单元，每个存储单元设置在第一线和第二线之间，并且具有串联连接的可变电阻元件和开关元件。 可变电阻元件包括可变电阻层，其被配置为在低电阻状态和高电阻状态之间改变其电阻值。 可变电阻层由过渡金属氧化物构成。 构成过渡金属氧化物的过渡金属和氧的比例沿着从第一线指向第二线的第一方向在1:1和1:2之间变化。
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