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    Efficient detection and response to spin waits in multi-processor virtual machines
    1.
    发明授权
    Efficient detection and response to spin waits in multi-processor virtual machines 有权
    在多处理器虚拟机中有效的检测和响应自旋等待

    公开(公告)号：US09201673B2

    公开(公告)日：2015-12-01

    申请号：US12182971

    申请日：2008-07-30

    申请人： Yau Ning Chin ,  Rene Antonio Vega ,  John Te-Jui Sheu ,  Arun Kishan ,  Thomas Fahrig

    发明人： Yau Ning Chin ,  Rene Antonio Vega ,  John Te-Jui Sheu ,  Arun Kishan ,  Thomas Fahrig

    IPC分类号： G06F9/455 ,  G06F9/52

    CPC分类号： G06F9/45558 ,  G06F9/45533 ,  G06F9/526 ,  G06F2009/4557

    摘要： Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.

    摘要翻译： 本文公开了用于在包括多个虚拟机和虚拟处理器的虚拟机环境中衰减自旋等待的各个方面。 选定的虚拟处理器可以被给定时间片扩展，以防止这种虚拟处理器变得不被调度（并且因此导致其他虚拟处理器必须旋转等待）。 也可以明确地调度所选择的虚拟处理器，使得它们可以被赋予更高的资源优先级，从而减少等待这些所选择的虚拟处理器的其他虚拟处理器的旋转等待。 最后，各种旋转等待检测技术可以被并入到时间片扩展中并且表达调度机制，以便识别潜在的和现有的旋转等待场景。

    Method and system for a second level address translation in a virtual machine environment
    5.
    发明授权
    Method and system for a second level address translation in a virtual machine environment 有权
    在虚拟机环境中进行二级地址转换的方法和系统

    公开(公告)号：US07428626B2

    公开(公告)日：2008-09-23

    申请号：US11075211

    申请日：2005-03-08

    申请人： Rene Antonio Vega

    发明人： Rene Antonio Vega

    IPC分类号： G06F9/34

    CPC分类号： G06F12/1036 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/109 ,  G06F12/145

    摘要： A method of performing a translation from a guest virtual address to a host physical address in a virtual machine environment includes receiving a guest virtual address from a host computer executing a guest virtual machine program and using the hardware oriented method of the host CPU to determine the guest physical address. A second level address translation to a host physical address is then performed. In one embodiment, a multiple tier tree is traversed which translates the guest physical address into a host physical address. In another embodiment, the second level of address translation is performed by employing a hash function of the guest physical address and a reference to a hash table. One aspect of the invention is the incorporation of access overrides associated with the host physical address which can control the access permissions of the host memory.

    摘要翻译： 在虚拟机环境中执行从客户虚拟地址到主机物理地址的转换的方法包括从执行客体虚拟机程序的主计算机接收来宾虚拟地址，并使用主机CPU的面向硬件的方法来确定 客人物理地址。 然后执行到主机物理地址的第二级地址转换。 在一个实施例中，遍历多层树，其将访客物理地址转换为主机物理地址。 在另一个实施例中，通过采用访客物理地址的散列函数和对散列表的引用来执行第二级地址转换。 本发明的一个方面是结合与主机物理地址相关联的访问覆盖，其可以控制主机存储器的访问许可。

    LOCK-FREE SCHEDULER WITH PRIORITY SUPPORT
    10.
    发明申请
    LOCK-FREE SCHEDULER WITH PRIORITY SUPPORT 审中-公开
    无优先安排，优先支持

    公开(公告)号：US20100251250A1

    公开(公告)日：2010-09-30

    申请号：US12414454

    申请日：2009-03-30

    申请人： Arun U. Kishan ,  Thomas D. I. Fahrig ,  Rene Antonio Vega

    发明人： Arun U. Kishan ,  Thomas D. I. Fahrig ,  Rene Antonio Vega

    IPC分类号： G06F9/46

    CPC分类号： G06F9/52 ,  G06F9/4843

    摘要： Techniques for implementing a lock-free scheduler with ordering support are described herein. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present disclosure. It can be appreciated by one of skill in the art that one or more various aspects of the disclosure may include but are not limited to circuitry and/or programming for effecting the herein-referenced aspects of the present disclosure; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the herein-referenced aspects depending upon the design choices of the system designer.

    摘要翻译： 本文描述了用于实现具有排序支持的无锁定调度器的技术。 除了上述之外，其他方面在形成本公开的一部分的权利要求，附图和文本中描述。 本领域技术人员可以理解，本公开的一个或多个各个方面可以包括但不限于用于实现本公开的本文参考的方面的电路和/或编程; 根据系统设计者的设计选择，电路和/或编程实际上可以是被配置为实现本文参考的方面的硬件，软件和/或固件的任何组合。