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公开(公告)号：US20140042552A1
公开(公告)日：2014-02-13
申请号：US13958592
申请日：2013-08-04
CPC分类号： H01L27/0617 , H01L21/28079 , H01L21/28114 , H01L21/823412 , H01L21/823462 , H01L27/088 , H01L29/42376 , H01L29/66492 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： Provided is a semiconductor device having an insulating gate field effect transistor equipped with a metal oxide film in a portion, on the side of a source region, between a gate insulating film and a gate electrode. The metal oxide film is provided above a p+ type semiconductor region for punch-through stopper so as to cover the entire region thereof. Such a metal oxide film contributes to a decrease in the impurity concentration of the p+ type semiconductor region, making it possible to reduce variations in the threshold voltage of the transistor. On the side of a drain region, the gate insulating film is formed as a single film without stacking the metal oxide film thereon. As a result, the resulting transistor can escape deterioration in reliability which will otherwise occur due to hot carriers on the side of the end of the drain region.
摘要翻译： 本发明提供一种具有绝缘栅场效应晶体管的半导体器件，该绝缘栅场效应晶体管在栅极绝缘膜和栅电极之间在源极区一侧部分具有金属氧化物膜。 金属氧化物膜设置在用于穿通止挡件的p +型半导体区域上方以覆盖其整个区域。 这种金属氧化物膜有助于p +型半导体区域的杂质浓度的降低，从而可以减小晶体管的阈值电压的变化。 在漏极区域侧，栅极绝缘膜形成为单层膜而不在其上堆叠金属氧化物膜。 结果，所得到的晶体管可以避免否则由于漏极区域端部的热载流子而导致的可靠性劣化。
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公开(公告)号：US09831259B2
公开(公告)日：2017-11-28
申请号：US15277996
申请日：2016-09-27
IPC分类号： H01L27/11563 , H01L27/1157 , H01L29/66 , H01L27/11568 , H01L27/11573 , H01L21/266 , H01L21/28 , H01L29/792 , H01L21/8234 , H01L29/78 , H01L23/535 , H01L29/06 , H01L29/36 , H01L29/423
CPC分类号： H01L27/1157 , H01L21/266 , H01L21/28282 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L23/535 , H01L27/11568 , H01L27/11573 , H01L29/0649 , H01L29/36 , H01L29/42344 , H01L29/66545 , H01L29/6659 , H01L29/66833 , H01L29/7833 , H01L29/792
摘要： Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode.
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公开(公告)号：US20130175611A1
公开(公告)日：2013-07-11
申请号：US13735857
申请日：2013-01-07
IPC分类号： H01L21/02 , H01L27/088
CPC分类号： H01L21/02697 , H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L21/823857 , H01L21/823878 , H01L27/088 , H01L27/0924
摘要： An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate.
摘要翻译： 降低了形成低电压场效应晶体管的区域的顶视图中的区域，并且降低了形成高电压场效应晶体管的区域的顶视图中的区域。 形成低电压场效应晶体管（第一nMIS和第一pMIS）的有源区域由从元件隔离部分的表面突出的半导体衬底的第一凸部和高电场电场效应晶体管的有源区域构成， 形成电压场效应晶体管（第二nMIS和第二pMIS）由半导体衬底的从元件隔离部分的表面突出的第二凸部和形成在半导体衬底中的沟槽部分构成。
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公开(公告)号：US09460929B2
公开(公告)日：2016-10-04
申请号：US14634736
申请日：2015-02-28
IPC分类号： H01L21/266 , H01L29/66 , H01L27/115 , H01L21/28 , H01L29/792 , H01L21/8234 , H01L29/78
CPC分类号： H01L27/1157 , H01L21/266 , H01L21/28282 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L23/535 , H01L27/11568 , H01L27/11573 , H01L29/0649 , H01L29/36 , H01L29/42344 , H01L29/66545 , H01L29/6659 , H01L29/66833 , H01L29/7833 , H01L29/792
摘要： Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode.
摘要翻译： 提供了具有改进的性能的半导体器件。 在半导体衬底上，通过第一绝缘膜形成虚拟控制栅电极。 在半导体衬底上，用于存储单元的存储栅电极经由具有内部电荷存储部分的第二绝缘膜形成，以便与虚拟控制栅电极相邻。 此时，存储栅电极的高度被调节为低于虚拟控制栅电极的高度。 然后，形成第三绝缘膜，以覆盖虚拟控制栅电极和存储栅电极。 然后，对第三绝缘膜进行抛光以露出虚拟控制栅电极。 此时，存储栅电极不露出。 然后，去除虚拟控制栅电极并用金属栅电极代替。
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公开(公告)号：US09184053B2
公开(公告)日：2015-11-10
申请号：US13735857
申请日：2013-01-07
IPC分类号： H01L27/092 , H01L27/088 , H01L21/70 , H01L21/8234 , H01L21/76 , H01L21/02 , H01L21/8238
CPC分类号： H01L21/02697 , H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L21/823857 , H01L21/823878 , H01L27/088 , H01L27/0924
摘要： An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate.
摘要翻译： 降低了形成低电压场效应晶体管的区域的顶视图中的区域，并且降低了形成高电压场效应晶体管的区域的顶视图中的区域。 形成低电压场效应晶体管（第一nMIS和第一pMIS）的有源区域由从元件隔离部分的表面突出的半导体衬底的第一凸部和高电场电场效应晶体管的有源区域构成， 形成电压场效应晶体管（第二nMIS和第二pMIS）由半导体衬底的从元件隔离部分的表面突出的第二凸部和形成在半导体衬底中的沟槽部分构成。
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公开(公告)号：US09054102B2
公开(公告)日：2015-06-09
申请号：US14329294
申请日：2014-07-11
IPC分类号： H01L29/51 , H01L27/088 , H01L29/66 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/512 , H01L21/8234 , H01L21/823462 , H01L21/823857 , H01L27/088 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66484
摘要： The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET.
摘要翻译： 提高了半导体器件的性能。 该器件包括第一MISFET，其中将铪添加到包括氮氧化硅的第一栅极绝缘膜的栅极电极侧，以及第二MISFET，其中在包括氮氧化硅的第二栅极绝缘膜的栅极电极侧添加铪。 将第二MISFET的第二栅极绝缘膜中的铪浓度设定为小于第一MISFET的第一栅极绝缘膜中的铪浓度; 并且将第二MISFET的第二栅极绝缘膜中的氮浓度设定为小于第一MISFET的第一栅极绝缘膜中的氮浓度。 结果，第二MISFET的阈值电压被调整为小于第一MISFET的阈值电压。
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公开(公告)号：US08809959B2
公开(公告)日：2014-08-19
申请号：US13693351
申请日：2012-12-04
IPC分类号： H01L27/088
CPC分类号： H01L29/512 , H01L21/8234 , H01L21/823462 , H01L21/823857 , H01L27/088 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66484
摘要： The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET.
摘要翻译： 提高了半导体器件的性能。 该器件包括第一MISFET，其中将铪添加到包括氮氧化硅的第一栅极绝缘膜的栅极电极侧，以及第二MISFET，其中在包括氮氧化硅的第二栅极绝缘膜的栅极电极侧添加铪。 将第二MISFET的第二栅极绝缘膜中的铪浓度设定为小于第一MISFET的第一栅极绝缘膜中的铪浓度; 并且将第二MISFET的第二栅极绝缘膜中的氮浓度设定为小于第一MISFET的第一栅极绝缘膜中的氮浓度。 结果，第二MISFET的阈值电压被调整为小于第一MISFET的阈值电压。
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