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公开(公告)号：US12080716B2
公开(公告)日：2024-09-03
申请号：US18317500
申请日：2023-05-15
IPC分类号： H01L27/12 , H01L29/66 , H01L29/78 , H01L21/8234 , H01L21/8238 , H01L29/417
CPC分类号： H01L27/1203 , H01L27/1207 , H01L29/66477 , H01L29/66628 , H01L29/66651 , H01L29/7834 , H01L21/823418 , H01L21/823814 , H01L29/41783
摘要： On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
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公开(公告)号：US11211406B2
公开(公告)日：2021-12-28
申请号：US15251238
申请日：2016-08-30
发明人： Ryuta Tsuchiya , Toshiaki Iwamatsu
IPC分类号： H01L27/12 , H01L21/84 , H01L27/11 , H03K17/687 , H01L29/06 , H01L21/8238 , H01L27/105
摘要： To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.
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公开(公告)号：US10756115B2
公开(公告)日：2020-08-25
申请号：US16670918
申请日：2019-10-31
IPC分类号： H01L21/8234 , H01L27/12 , H01L29/66 , H01L29/78 , H01L29/417 , H01L21/8238
摘要： On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
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公开(公告)号：US10510775B2
公开(公告)日：2019-12-17
申请号：US15695410
申请日：2017-09-05
IPC分类号： H01L29/06 , H01L27/12 , H01L29/66 , H01L29/78 , H01L21/8234 , H01L29/417 , H01L21/8238
摘要： On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
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公开(公告)号：US09978839B2
公开(公告)日：2018-05-22
申请号：US15628925
申请日：2017-06-21
IPC分类号： H01L21/00 , H01L29/10 , H01L29/78 , H01L29/06 , H01L21/74 , H01L29/66 , H01L21/265 , H01L21/8238 , H01L21/84
CPC分类号： H01L29/1083 , H01L21/265 , H01L21/74 , H01L21/76897 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/0878 , H01L29/41783 , H01L29/4238 , H01L29/66477 , H01L29/665 , H01L29/66537 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66742 , H01L29/66757 , H01L29/66772 , H01L29/7824 , H01L29/7833 , H01L29/78606 , H01L29/78621 , H01L29/78651 , H01L29/78654
摘要： Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
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公开(公告)号：US09515170B2
公开(公告)日：2016-12-06
申请号：US15017459
申请日：2016-02-05
发明人： Toshiaki Iwamatsu , Takashi Terada , Hirofumi Shinohara , Kozo Ishikawa , Ryuta Tsuchiya , Kiyoshi Hayashi
IPC分类号： H01L29/66 , H01L21/28 , H01L29/78 , H01L21/308 , H01L21/321 , H01L21/265
CPC分类号： H01L29/66795 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/28035 , H01L21/3081 , H01L21/3086 , H01L21/321 , H01L29/785
摘要： An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.
摘要翻译： 本发明的目的是提供一种半导体器件，其具有通过以高精度形成鳍状半导体部分和栅极电极或通过改善元件之间的特性变化而具有优异的特性的鳍型晶体管。 本发明是一种半导体器件，包括：鳍状半导体部分，其一侧形成有源极区域，在其另一侧形成有漏极区域，以及形成在源极区域和漏极区域之间的栅电极， 翅片状半导体部分，其间具有栅极绝缘膜。 解决根据本发明的问题的一种解决方案是栅电极使用可湿蚀刻的金属材料或硅化物材料。
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公开(公告)号：US09024386B2
公开(公告)日：2015-05-05
申请号：US13678103
申请日：2012-11-15
IPC分类号： H01L21/00 , H01L29/78 , H01L21/48 , H01L21/84 , H01L27/02 , H01L27/12 , H01L21/768 , H01L29/786 , H01L21/74
CPC分类号： H01L21/84 , H01L21/28008 , H01L21/283 , H01L21/31111 , H01L21/486 , H01L21/743 , H01L21/76802 , H01L21/76831 , H01L21/76895 , H01L21/76897 , H01L27/0207 , H01L27/1203 , H01L29/66568 , H01L29/78 , H01L29/78648 , H01L29/78654 , H01L2924/0002 , H01L2924/00
摘要： Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.
摘要翻译： 提高了半导体器件的特性。 本发明的半导体器件包括：（a）布置在由元件隔离区包围的半导体区域形成的有源区中的MISFET; 和（b）布置在有源区下方的绝缘层。 此外，半导体器件包括：（c）布置在有源区下方以插入绝缘层的p型半导体区域; 和（d）布置在p型半导体区域下方的导电类型与p型相反的n型半导体区域。 并且，p型半导体区域包括从绝缘层的下方延伸的连接区域，并且MIS型的p型半导体区域和栅极电极通过作为一体形成的导电膜的共享插头彼此连接 从栅电极上方延伸到连接区域的上方。
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公开(公告)号：US08941178B2
公开(公告)日：2015-01-27
申请号：US13747537
申请日：2013-01-23
IPC分类号： H01L27/12 , H01L29/786 , H01L29/66
CPC分类号： H01L29/1083 , H01L21/265 , H01L21/74 , H01L21/76897 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/0878 , H01L29/41783 , H01L29/4238 , H01L29/66477 , H01L29/665 , H01L29/66537 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66742 , H01L29/66757 , H01L29/66772 , H01L29/7824 , H01L29/7833 , H01L29/78606 , H01L29/78621 , H01L29/78651 , H01L29/78654
摘要： Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
摘要翻译： 防止在SOI衬底上发生MOSFET的短沟道特性和寄生电容。 在SOI衬底上的栅电极的侧壁上形成具有通过依次层叠氧化硅膜和氮化物膜而获得的堆叠结构的侧壁。 随后，在栅极旁边形成外延层之后，去除氮化物膜。 然后，使用栅电极和外延层作为掩模，将杂质注入到半导体衬底的上表面中，使得仅在半导体衬底的上表面的正下方形成晕圈区域 栅电极的两端附近。
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公开(公告)号：US20130230964A1
公开(公告)日：2013-09-05
申请号：US13781737
申请日：2013-02-28
发明人： Akira Imai , Toshiaki Iwamatsu , Akihiro Nakae
CPC分类号： H01L21/76 , H01L21/31053 , H01L21/31056 , H01L21/68 , H01L21/76229 , H01L21/76283 , H01L23/544 , H01L27/1207 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a semiconductor integrated circuit device includes the step of forming an SOI device region and a bulk device region on an SOI type semiconductor wafer. The method includes: removing a BOX layer and an SOI layer in a bulk device region; and thereafter forming an STI region in both the SOI device region and the bulk device region. In the method, the STI region in the SOI device region is formed to extend through the BOX layer.
摘要翻译： 制造半导体集成电路器件的方法包括在SOI型半导体晶片上形成SOI器件区域和体器件区域的步骤。 该方法包括：去除大容量器件区域中的BOX层和SOI层; 然后在SOI器件区域和本体器件区域中形成STI区域。 在该方法中，SOI器件区域中的STI区域形成为延伸穿过BOX层。
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公开(公告)号：US20130175611A1
公开(公告)日：2013-07-11
申请号：US13735857
申请日：2013-01-07
IPC分类号： H01L21/02 , H01L27/088
CPC分类号： H01L21/02697 , H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L21/823857 , H01L21/823878 , H01L27/088 , H01L27/0924
摘要： An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate.
摘要翻译： 降低了形成低电压场效应晶体管的区域的顶视图中的区域，并且降低了形成高电压场效应晶体管的区域的顶视图中的区域。 形成低电压场效应晶体管（第一nMIS和第一pMIS）的有源区域由从元件隔离部分的表面突出的半导体衬底的第一凸部和高电场电场效应晶体管的有源区域构成， 形成电压场效应晶体管（第二nMIS和第二pMIS）由半导体衬底的从元件隔离部分的表面突出的第二凸部和形成在半导体衬底中的沟槽部分构成。
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