公开(公告)号：US09231096B2

公开(公告)日：2016-01-05

申请号：US14550118

申请日：2014-11-21

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota

IPC: H01L29/00 ,  H01L29/778 ,  H01L29/205 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/201 ,  H01L29/51

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1−zAlzN (0≦z≦1), a channel layer having a composition of: AlxGa1−xN (0≦x≦1) or InyGa1−yN (0≦y≦1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.

Abstract translation: 场效应晶体管包括衬底和设置在衬底上的半导体层，其中半导体层包括设置在衬底上的下阻挡层，生长Ga面，晶格弛豫并具有组成In 1-z Al z N（0＆nl; z＆nl E; 1），具有以下组成的沟道层：Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）或In y Ga 1-y N（0＆nlE; y＆nlE; 1）。 或提供在栅极绝缘膜上并与栅极绝缘膜配置的栅电极，栅极配置在栅极绝缘膜上，栅电极配置在栅极绝缘膜上， 位于源电极和漏电极之间的区域。

公开(公告)号：US20180233590A1

公开(公告)日：2018-08-16

申请号：US15923787

申请日：2018-03-16

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/06 ,  H01L29/15 ,  H01L29/205

CPC classification number: H01L29/7783 ,  H01L29/0607 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7787

Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≥5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

公开(公告)号：US09768257B2

公开(公告)日：2017-09-19

申请号：US14153203

申请日：2014-01-13

Applicant: Renesas Electronics Corporation

Inventor： Kazuki Ota ,  Yuji Ando

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/778 ,  H01L29/40 ,  H01L29/20

CPC classification number: H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/7787

Abstract: A high electron mobility transistor having a channel layer, electron supply layer, source electrode, and drain electrode is included so as to have a cap layer formed on the electron supply layer between the source and drain electrodes and having an inclined side surface, an insulating film having an opening portion on the upper surface of the cap layer and covering the side surface thereof, and a gate electrode is formed in the opening portion and extending, via the insulating film, over the side surface of the cap layer on the drain electrode side. The gate electrode having an overhang on the drain electrode side can reduce the peak electric field.

公开(公告)号：US09954087B2

公开(公告)日：2018-04-24

申请号：US14470403

申请日：2014-08-27

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/15 ,  H01L29/20 ,  H01L29/423 ,  H01L29/205

CPC classification number: H01L29/7783 ,  H01L29/0607 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7787

Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≥5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

公开(公告)号：US08907349B2

公开(公告)日：2014-12-09

申请号：US13872914

申请日：2013-04-29

Applicant: Renesas Electronics Corporation

Inventor： Yuji Ando ,  Kazuki Ota

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/205 ,  H01L29/43 ,  H01L29/66 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L29/778 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7786

Abstract: In a high electron mobility transistor, with a normally-off operation maintained, on-resistance can be sufficiently reduced, so that the performance of a semiconductor device including the high electron mobility transistor is improved. Between a channel layer and an electron supply layer, a spacer layer whose band gap is larger than the band gap of the electron supply layer is provided. Thereby, due to the fact that the band gap of the spacer layer is large, a high potential barrier (electron barrier) is formed in the vicinity of an interface between the channel and the electron supply layer.

Abstract translation: 在高电子迁移率晶体管中，保持常关断操作，可以充分降低导通电阻，从而提高包括高电子迁移率晶体管的半导体器件的性能。 在沟道层和电子供给层之间设置带隙大于电子供给层的带隙的间隔层。 因此，由于间隔层的带隙大，所以在沟道与电子供给层的界面附近形成高电位势垒（电子势垒）。

公开(公告)号：US09530879B2

公开(公告)日：2016-12-27

申请号：US14947172

申请日：2015-11-20

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota

IPC: H01L29/00 ,  H01L29/778 ,  H01L29/205 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/201 ,  H01L29/51

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A semiconductor device including a field effect transistor including a substrate, a lower barrier layer provided on the substrate, a channel layer provided on the lower barrier layer, an electron supplying layer provided on the channel layer, a source electrode and a drain electrode provided on the electron layer, and a gate electrode provided between the source electrode and the drain electrode. The lower barrier layer includes a composition of In1-zAlzN (0≦z≦1). The channel layer includes a composition of AlxGa1-xN (0≦x≦1). A recess is provided in a region between the source electrode and the drain electrode, wherein the recess goes through the electron supplying layer to a depth that exposes the channel layer, and the gate electrode is disposed on a gate insulating film that covers a bottom surface and an inner wall surface of the recess.

Abstract translation: 一种包括场效应晶体管的半导体器件，包括衬底，设置在衬底上的下阻挡层，设置在下阻挡层上的沟道层，设置在沟道层上的电子供给层，设置在沟道层上的源电极和漏电极 电子层和设置在源电极和漏电极之间的栅电极。 下阻挡层包括In1-zAlzN（0≤z≤1）的组成。 沟道层包括Al x Ga 1-x N（0≤x≤1）的组成。 在源电极和漏电极之间的区域设置有凹部，其中，凹部穿过电子供给层到达暴露沟道层的深度，并且栅电极设置在覆盖底面的栅极绝缘膜上 和凹部的内壁表面。

公开(公告)号：US20140367743A1

公开(公告)日：2014-12-18

申请号：US14470403

申请日：2014-08-27

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/7783 ,  H01L29/0607 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7787

Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≧5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

Abstract translation: 在III族氮化物型场效应晶体管中，本发明通过缓冲层中的残留载流子的传导来减少漏电流成分，并且可以实现击穿电压的提高，并且提高了载流子限制效应（载流子限制） 提高夹断特性的通道（抑制短路效应）。 例如，当将本发明应用于GaN型场效应晶体管时，除了沟道层的GaN之外，使用其中铝组成逐渐或逐步朝向顶部的组分调制（组成梯度）AlGaN层用作 缓冲层（杂质缓冲液）。 对于要制备的FET的栅极长度Lg，选择电子供给层和沟道层的层厚度的和a以满足Lg /a≥5，并且在这种情况下，沟道的层厚度 只要在室温下积聚在通道层中的二维电子气的德布罗意波长，不超过5倍（约500）的范围内选择层。