公开(公告)号：US20130307082A1

公开(公告)日：2013-11-21

申请号：US13860813

申请日：2013-04-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenzo MANABE

IPC: H01L29/423 ,  H01L29/40

CPC classification number: H01L29/42372 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/78

Abstract: Improved formation of replacement metal gate transistors is obtained by utilizing a silicon to metal substitution reaction. After removing the dummy gate, a gate dielectric and work function metal are deposited. The work function metal is deposited to a different thickness for the P-channel transistors than for the N-channel transistors. A sacrificial polysilicon gate is then formed, which is caused to undergo substitution with a metal such as aluminum.

Abstract translation: 通过利用硅与金属的取代反应可以获得更换的金属栅极晶体管的形成。 在去除虚拟栅极之后，沉积栅极电介质和功函数金属。 对于P沟道晶体管，功函数金属沉积到不同于N沟道晶体管的厚度。 然后形成牺牲多晶硅栅极，其被用铝等金属进行取代。

公开(公告)号：US20160141030A1

公开(公告)日：2016-05-19

申请号：US14945321

申请日：2015-11-18

Applicant: Renesas Electronics Corporation

Inventor： Kiyoshi TAKEUCHI ,  Akira TANABE ,  Kenzo MANABE

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C2013/0073 ,  G11C2013/0076 ,  G11C2013/0092 ,  G11C2213/79 ,  G11C2213/82

Abstract: A semiconductor memory device has at least one memory cell using a resistance variable element, and a control circuit which controls writing to and reading from the memory cell. Operations by the control circuit include a first writing operation, a second writing operation, and a rewriting operation. The first writing operation is a writing operation for applying a first voltage of a first polarity to the memory cell. The second writing operation is a writing operation for applying a second voltage of a second polarity opposite to the first polarity to the memory cell. The rewriting operation is a writing operation for, when the first writing operation fails, further executing a second A writing operation for applying the second voltage of the second polarity to the memory cell and a first A writing operation for applying the first voltage of the first polarity to the memory cell.

Abstract translation: 半导体存储器件具有使用电阻可变元件的至少一个存储单元，以及控制对存储单元写入和读取的控制电路。 由控制电路进行的操作包括第一写入操作，第二写入操作和重写操作。 第一写入操作是用于将第一极性的第一电压施加到存储器单元的写入操作。 第二写入操作是将与第一极性相反的第二极性的第二电压施加到存储单元的写入操作。 重写操作是写入操作，当第一写入操作失败时，进一步执行用于将第二极性的第二电压施加到存储单元的第二A写入操作，以及用于施加第一写入操作的第一电压的第一A写入操作 极性到存储单元。

公开(公告)号：US20150056778A1

公开(公告)日：2015-02-26

申请号：US14516164

申请日：2014-10-16

Applicant: Renesas Electronics Corporation

Inventor： Kenzo MANABE ,  Naoya INOUE ,  Kenichiro HIJIOKA ,  Yoshihiro HAYASHI

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L27/1085 ,  H01L21/768 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.

Abstract translation: 一种半导体器件，包括：多层布线层，位于基板的上方，其中堆叠由布线和绝缘层构成的多个布线层; 存储电路，其形成在所述基板的存储电路区域中，并且具有嵌入在位于所述多层布线层中的凹部的电容元件; 形成在基板的逻辑电路区域中的逻辑电路; 层叠在由下部电极，电容绝缘膜和上部电极构成的电容元件上的上部耦合布线; 以及形成在构成逻辑电路的布线的上表面上的盖层。 上部连接线的上表面和盖膜的上表面设置在同一平面上。

公开(公告)号：US20140239407A1

公开(公告)日：2014-08-28

申请号：US14187745

申请日：2014-02-24

Applicant: International Business Machines Corporation ,  Renesas Electronics Corporation

Inventor： Kenzo MANABE ,  Hemanth JAGANNATHAN

IPC: H01L27/092 ,  H01L27/11 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/11

Abstract: A method and structure for a semiconductor device includes a semiconductor substrate and an N-channel transistor and a P-channel transistor provided on the semiconductor substrate. Each of the N-channel transistor and the P-channel transistor has a gate dielectric film on the semiconductor substrate, and a gate electrode is formed on the gate dielectric. The gate electrode comprises a metal conductive layer. The oxygen concentration in the metal conductive layer for the N-channel transistor is different from that for the P-channel transistor.

Abstract translation: 半导体器件的方法和结构包括半导体衬底和设置在半导体衬底上的N沟道晶体管和P沟道晶体管。 N沟道晶体管和P沟道晶体管中的每一个在半导体衬底上具有栅极电介质膜，栅电极形成在栅极电介质上。 栅电极包括金属导电层。 用于N沟道晶体管的金属导电层中的氧浓度与P沟道晶体管的氧浓度不同。