公开(公告)号：US20160267975A1

公开(公告)日：2016-09-15

申请号：US14964383

申请日：2015-12-09

Applicant: Renesas Electronics Corporation

Inventor： Kiyoshi TAKEUCHI ,  Takashi Hase

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0073 ,  G11C2013/0076 ,  G11C2013/0092 ,  G11C2213/82

Abstract: A semiconductor memory includes a memory cell including a resistance change element and a control circuit configured to perform OFF-write processing of applying an OFF-write pulse to the memory cell for switching the state of the memory cell to a high-resistive state where a resistance value of the resistance change element is at least a first reference value and ON-write processing of applying an ON-write pulse to the memory cell for switching the state of the memory cell to a low-resistive state where the resistance value is less than a second reference value. The control circuit performs the OFF-write processing by applying an auxiliary pulse which is smaller than the OFF-write pulse in voltage amplitude to the memory cell one or more time(s) after having applied the OFF-write pulse to the memory cell.

Abstract translation: 半导体存储器包括具有电阻变化元件和控制电路的存储单元，该存储单元被配置为执行向存储单元施加OFF写入脉冲以将存储单元的状态切换到高电阻状态的OFF写入处理，其中， 电阻变化元件的电阻值至少为第一基准值，以及对存储单元施加导通写入脉冲以将存储单元的状态切换到电阻值较小的低电阻状态的ON-写入处理 比第二参考值。 控制电路通过在向存储单元施加了写 - 写脉冲之后，向存储单元施加小于电压幅度的OFF写入脉冲的辅助脉冲来执行OFF写入处理。

公开(公告)号：US20160056207A1

公开(公告)日：2016-02-25

申请号：US14809106

申请日：2015-07-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshiharu NAGUMO ,  Kiyoshi TAKEUCHI ,  Toyoji YAMAMOTO

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/146 ,  H01L45/16

Abstract: Disclosed is a semiconductor device that reduces the area of a transistor in a ReRAM. A plurality of memory cells differ from each other in the combination of bit line and plate line. The potential of plate line PL2 is a forming voltage. By contrast, the potentials of the other plate lines are +Vi. The potential of bit line BL2 is 0 V (ground potential). By contrast, the potentials of the other bit lines are +Vi. The potential of is +Vgf. By contrast, the potentials of the other word lines are +Vi.

Abstract translation: 公开了减少ReRAM中晶体管面积的半导体器件。 在位线和板线的组合中，多个存储单元彼此不同。 板线PL2的电位为成形电压。 相反，其他板条的电位为+ Vi。 位线BL2的电位为0V（地电位）。 相反，其他位线的电位为+ Vi。 是+ Vgf的潜力。 相反，其他字线的电位为+ Vi。

公开(公告)号：US20160141030A1

公开(公告)日：2016-05-19

申请号：US14945321

申请日：2015-11-18

Applicant: Renesas Electronics Corporation

Inventor： Kiyoshi TAKEUCHI ,  Akira TANABE ,  Kenzo MANABE

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C2013/0073 ,  G11C2013/0076 ,  G11C2013/0092 ,  G11C2213/79 ,  G11C2213/82

Abstract: A semiconductor memory device has at least one memory cell using a resistance variable element, and a control circuit which controls writing to and reading from the memory cell. Operations by the control circuit include a first writing operation, a second writing operation, and a rewriting operation. The first writing operation is a writing operation for applying a first voltage of a first polarity to the memory cell. The second writing operation is a writing operation for applying a second voltage of a second polarity opposite to the first polarity to the memory cell. The rewriting operation is a writing operation for, when the first writing operation fails, further executing a second A writing operation for applying the second voltage of the second polarity to the memory cell and a first A writing operation for applying the first voltage of the first polarity to the memory cell.

Abstract translation: 半导体存储器件具有使用电阻可变元件的至少一个存储单元，以及控制对存储单元写入和读取的控制电路。 由控制电路进行的操作包括第一写入操作，第二写入操作和重写操作。 第一写入操作是用于将第一极性的第一电压施加到存储器单元的写入操作。 第二写入操作是将与第一极性相反的第二极性的第二电压施加到存储单元的写入操作。 重写操作是写入操作，当第一写入操作失败时，进一步执行用于将第二极性的第二电压施加到存储单元的第二A写入操作，以及用于施加第一写入操作的第一电压的第一A写入操作 极性到存储单元。

公开(公告)号：US20160005792A1

公开(公告)日：2016-01-07

申请号：US14750060

申请日：2015-06-25

Applicant: Renesas Electronics Corporation

Inventor： Makoto UEKI ,  Nobuyuki IKARASHI ,  Jun KAWAHARA ,  Kiyoshi TAKEUCHI ,  Takashi HASE

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1658

Abstract: Provided is a semiconductor memory device (resistance random access memory element) improved in properties. A Ru film is formed as a film of a lower electrode by sputtering, and a Ta film is formed thereonto by sputtering. Next, the Ta film is oxidized with plasma to oxidize the Ta film. In this way, a compound Ta2O5 is produced and further Ru is diffused into the compound to form a layer (variable resistance layer) in which Ru is diffused into the compound Ta2O5. Such an incorporation of a metal (such as Ru) into a transition metal oxide TMO (such as Ta2O5) makes it possible to form electron conductive paths additional to filaments to lower the filaments in density and thickness. Thus, the memory element can be restrained from undergoing OFF-fixation, by which the element is not easily lowered in resistance, to be improved in ON-properties.

Abstract translation: 提供了一种改进了性能的半导体存储器件（电阻随机存取存储元件）。 通过溅射形成作为下电极的膜的Ru膜，并通过溅射在其上形成Ta膜。 接着，用等离子体氧化Ta膜，氧化Ta膜。 以这种方式，产生化合物Ta 2 O 5，并且进一步将Ru扩散到化合物中以形成其中Ru扩散到化合物Ta 2 O 5中的层（可变电阻层）。 金属（例如Ru）的这种引入到过渡金属氧化物TMO（例如Ta 2 O 5）中使得有可能形成除了长丝之外的电子传导路径以降低细丝的密度和厚度。 因此，可以抑制存储元件的导通性能的提高，使得元件不易于降低电阻的非固定。

公开(公告)号：US20150279923A1

公开(公告)日：2015-10-01

申请号：US14661043

申请日：2015-03-18

Applicant: Renesas Electronics Corporation

Inventor： Makoto UEKI ,  Kiyoshi TAKEUCHI ,  Takashi HASE

IPC: H01L49/02 ,  H01L23/532 ,  H01L27/06 ,  H01L23/522

CPC classification number: H01L28/65 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/0629 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To provide a semiconductor device having less variation in characteristics. The semiconductor device is equipped with a plug formed in an interlayer insulating film, a lower electrode provided on the plug and to be coupled to the plug, a middle layer provided on the lower electrode and made of a metal oxide, and an upper electrode provided on the middle layer. The middle layer has a layered region contiguous to the lower electrode and the upper electrode. At least a portion of the layered region does not overlap with the plug. At least a portion of the plug does not overlap with the layered region.

Abstract translation: 提供具有较小的特性变化的半导体器件。 半导体器件配备有形成在层间绝缘膜中的插塞，设置在插塞上并与插头耦合的下电极，设置在下电极上并由金属氧化物制成的中间层，以及上电极 在中间层。 中间层具有与下部电极和上部电极邻接的分层区域。 层叠区域的至少一部分不与插头重叠。 塞子的至少一部分不与分层区域重叠。