公开(公告)号：US09837492B2

公开(公告)日：2017-12-05

申请号：US15079338

申请日：2016-03-24

Applicant: Renesas Electronics Corporation

Inventor： Wataru Sumida ,  Akihiro Shimomura

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a vertical MOSFET in which bottom portions of each gate electrode formed in a ditch are extended toward the drain region, the on resistance is reduced while preventing voltage resistance reduction and switching speed reduction caused by a capacitance increase between the gate and drain. A vertical MOSFET includes first ditches, second ditches, and gate electrodes. The first ditches are formed in an upper surface portion of an epitaxial layer formed over a semiconductor substrate and extend in a second direction extending along a main surface of the semiconductor substrate. The second ditches are formed in bottom surface portions of each of the first ditches and are arranged in the second direction. The gate electrodes are formed in the first ditches and second ditches. The gate electrodes formed in the first ditches include lower electrodes arranged in the second direction.

公开(公告)号：US20160336443A1

公开(公告)日：2016-11-17

申请号：US15079338

申请日：2016-03-24

Applicant: Renesas Electronics Corporation

Inventor： Wataru Sumida ,  Akihiro Shimomura

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a vertical MOSFET in which bottom portions of each gate electrode formed in a ditch are extended toward the drain region, the on resistance is reduced while preventing voltage resistance reduction and switching speed reduction caused by a capacitance increase between the gate and drain. A vertical MOSFET includes first ditches, second ditches, and gate electrodes. The first ditches are formed in an upper surface portion of an epitaxial layer formed over a semiconductor substrate and extend in a second direction extending along a main surface of the semiconductor substrate. The second ditches are formed in bottom surface portions of each of the first ditches and are arranged in the second direction. The gate electrodes are formed in the first ditches and second ditches. The gate electrodes formed in the first ditches include lower electrodes arranged in the second direction.

Abstract translation: 在形成沟槽的各栅电极的底部朝向漏极区域延伸的垂直MOSFET中，导通电阻降低，同时防止由栅极和漏极之间的电容增加引起的电阻降低和开关速度降低。 垂直MOSFET包括第一沟道，第二沟道和栅电极。 第一沟槽形成在形成在半导体衬底上的外延层的上表面部分中，并沿着沿着半导体衬底的主表面延伸的第二方向延伸。 第二沟槽形成在每个第一沟槽的底表面部分中并且沿第二方向布置。 栅电极形成在第一沟渠和第二沟渠中。 形成在第一沟槽中的栅电极包括沿第二方向布置的下电极。

公开(公告)号：US11043585B2

公开(公告)日：2021-06-22

申请号：US16374283

申请日：2019-04-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Wataru Sumida

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: Reliability of a semiconductor device is improved. The semiconductor device including a first MISFET group of a plurality of first MISFETs and a second MISFET group of a plurality of second MISFETs has a plurality of trenches each formed in a semiconductor layer and formed of an upper trench part and a lower trench part, and a plurality of gate electrodes formed inside the plurality of trenches. A thinner gate insulator is formed to the upper trench part and a thicker field insulator is formed to the lower trench part. In a trench at the outermost position in the first MISFET group and a trench at the outermost position in the second MISFET group, the gate insulator is not formed in the upper trench part, but the field insulator is formed in the upper trench part and the lower trench part.

公开(公告)号：US10170556B2

公开(公告)日：2019-01-01

申请号：US15797519

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Wataru Sumida ,  Akihiro Shimomura

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor device manufacturing method includes preparing a semiconductor substrate of a first conductivity type, forming a semiconductor layer of the first conductivity type over a main surface of the semiconductor substrate, forming a plurality of first ditches in an upper surface portion of the semiconductor layer such that the first ditches are arranged in a first direction extending along an upper surface of the semiconductor substrate, forming a plurality of second ditches in bottom surface portions of each of the first ditches such that the second ditches are arranged in a second direction perpendicular to the first direction, and covering a side wall of each of the first ditches with a first insulating film and a side wall and a bottom surface of each of the second ditches with a second insulating film thicker than the first insulating film.

公开(公告)号：US20130341708A1

公开(公告)日：2013-12-26

申请号：US13913147

申请日：2013-06-07

Applicant: Renesas Electronics Corporation

Inventor： Wataru Sumida

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813

Abstract: A low concentration P-type impurity (LCPI) layer situated over a drain layer has an impurity concentration lower than the drain layer. An N-type impurity base layer is situated over the LCPI layer. A gate insulating film is formed on the lateral side of a trench. A bottom insulation film formed to the bottom and lower portion on the lateral side of the trench has a larger thickness than the gate insulating film. A gate electrode is filled in the trench. At a cross section in the direction of the thickness including the bottom of the trench, a profile of the P-type impurity concentration is substantially constant and the difference between the maximum and minimum values is 10% or less of the average value for the maximum and minimum values. Further, the profile has a maximal value and a minimal value situated from the maximal value to the drain layer.

Abstract translation: 位于漏极层以上的低浓度P型杂质（LCPI）层的杂质浓度低于漏极层。 N型杂质基层位于LCPI层上。 栅极绝缘膜形成在沟槽的侧面上。 形成在沟槽的横向侧的底部和下部的底部绝缘膜具有比栅极绝缘膜更大的厚度。 栅电极填充在沟槽中。 在包括沟槽底部的厚度方向的横截面中，P型杂质浓度的曲线基本上是恒定的，最大值和最小值之间的差为最大值的平均值的10％以下 和最小值。 此外，轮廓具有从最大值到漏极层的最大值和最小值。