公开(公告)号：US09747990B2

公开(公告)日：2017-08-29

申请号：US15167596

申请日：2016-05-27

Applicant: Renesas Electronics Corporation

Inventor： Masamichi Fujito ,  Hiroshi Yoshida ,  Takanori Takahashi ,  Yasuhiko Taito

IPC: G11C16/20 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/20 ,  G11C16/0416 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3459 ,  G11C16/3481

Abstract: A semiconductor device includes a memory array having a plurality of complementary cells, each including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, and a control circuit for initializing the complementary cells. The control circuit performs a first initialization control of reducing the threshold voltage of both the first memory element and the second memory element of the complementary cell and changing the threshold voltage of at least one of the first memory element and the second memory element at an intermediate level lower than a first writing level and higher than an initialization level, a first writing control of changing the threshold voltage of one of the first memory element and the second memory element of the complementary cell at the first writing level, and a second initialization control of changing the threshold voltage of both the first memory element and the second memory element of the complementary cell at the initialization level.

公开(公告)号：US10366758B2

公开(公告)日：2019-07-30

申请号：US15900516

申请日：2018-02-20

Applicant: Renesas Electronics Corporation

Inventor： Takashi Kurafuji ,  Tomoya Ogawa ,  Yasuhiko Taito

IPC: G11C16/28 ,  G11C16/04 ,  G11C7/06 ,  G11C7/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/10 ,  G11C16/14

Abstract: A storage device includes a data memory unit and a status memory unit. The data memory unit includes a pair of flash memory cells to be read by a complementary read mode, and 1-bit data is stored therein by the pair of flash memory cells. The status memory unit includes a flash memory cell to be read by a reference read mode, and a status flag is stored therein by the flash memory cell.

公开(公告)号：US20170330630A1

公开(公告)日：2017-11-16

申请号：US15667487

申请日：2017-08-02

Applicant: Renesas Electronics Corporation

Inventor： Masamichi Fujito ,  Hiroshi Yoshida ,  Takanori Takahashi ,  Yasuhiko Taito

IPC: G11C16/20 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/20 ,  G11C16/0416 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3459 ,  G11C16/3481

Abstract: A controlling method of a semiconductor device provided with a memory array including a plurality of complementary cells, each cell including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, the controlling method comprising: performing a prewrite procedure that writes ‘0’ or ‘1’ to both of the first memory element and the second memory element.

公开(公告)号：US10102913B2

公开(公告)日：2018-10-16

申请号：US15667487

申请日：2017-08-02

Applicant: Renesas Electronics Corporation

Inventor： Masamichi Fujito ,  Hiroshi Yoshida ,  Takanori Takahashi ,  Yasuhiko Taito

IPC: G11C16/20 ,  G11C16/34 ,  G11C16/32 ,  G11C16/30

Abstract: A controlling method of a semiconductor device provided with a memory array including a plurality of complementary cells, each cell including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, the controlling method comprising: performing a prewrite procedure that writes ‘0’ or ‘1’ to both of the first memory element and the second memory element.