-
公开(公告)号：US09747990B2
公开(公告)日：2017-08-29
申请号：US15167596
申请日：2016-05-27
Applicant: Renesas Electronics Corporation
Inventor： Masamichi Fujito , Hiroshi Yoshida , Takanori Takahashi , Yasuhiko Taito
CPC classification number: G11C16/20 , G11C16/0416 , G11C16/0425 , G11C16/10 , G11C16/30 , G11C16/32 , G11C16/3459 , G11C16/3481
Abstract: A semiconductor device includes a memory array having a plurality of complementary cells, each including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, and a control circuit for initializing the complementary cells. The control circuit performs a first initialization control of reducing the threshold voltage of both the first memory element and the second memory element of the complementary cell and changing the threshold voltage of at least one of the first memory element and the second memory element at an intermediate level lower than a first writing level and higher than an initialization level, a first writing control of changing the threshold voltage of one of the first memory element and the second memory element of the complementary cell at the first writing level, and a second initialization control of changing the threshold voltage of both the first memory element and the second memory element of the complementary cell at the initialization level.
-
公开(公告)号：US10102913B2
公开(公告)日：2018-10-16
申请号：US15667487
申请日：2017-08-02
Applicant: Renesas Electronics Corporation
Inventor： Masamichi Fujito , Hiroshi Yoshida , Takanori Takahashi , Yasuhiko Taito
Abstract: A controlling method of a semiconductor device provided with a memory array including a plurality of complementary cells, each cell including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, the controlling method comprising: performing a prewrite procedure that writes ‘0’ or ‘1’ to both of the first memory element and the second memory element.
-
公开(公告)号：US20170330630A1
公开(公告)日：2017-11-16
申请号：US15667487
申请日：2017-08-02
Applicant: Renesas Electronics Corporation
Inventor： Masamichi Fujito , Hiroshi Yoshida , Takanori Takahashi , Yasuhiko Taito
CPC classification number: G11C16/20 , G11C16/0416 , G11C16/0425 , G11C16/10 , G11C16/30 , G11C16/32 , G11C16/3459 , G11C16/3481
Abstract: A controlling method of a semiconductor device provided with a memory array including a plurality of complementary cells, each cell including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, the controlling method comprising: performing a prewrite procedure that writes ‘0’ or ‘1’ to both of the first memory element and the second memory element.
-
公开(公告)号：US20130313637A1
公开(公告)日：2013-11-28
申请号：US13859243
申请日：2013-04-09
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Hiroshi Yoshida
IPC: H01L27/088 , H01L21/28
CPC classification number: H01L27/088 , H01L21/28008 , H01L21/823821 , H01L21/823828 , H01L27/0924 , H01L29/1037 , H01L29/4236 , H01L29/7834
Abstract: A transistor having a source region, a drain region, a plurality of trenches extended in the longitudinal direction of a channel between the source region and the drain region and arranged in parallel in a longitudinal direction of a channel, an epitaxial layer formed on the lateral surfaces of each of the trenches, a gate oxide film covering the epitaxial layer and a gate electrode covering the gate insulating film and filled in the trenches.
Abstract translation: 一种晶体管，具有源极区域，漏极区域，在源极区域和漏极区域之间的沟道的纵向方向上延伸并且沿沟道的纵向平行布置的多个沟槽，形成在侧面上的外延层 每个沟槽的表面，覆盖外延层的栅极氧化膜和覆盖栅极绝缘膜并填充在沟槽中的栅电极。
-
-
-
Search Results
4
records
(took 0.014 seconds)
