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公开(公告)号：US11515880B2
公开(公告)日：2022-11-29
申请号：US17319856
申请日：2021-05-13
发明人： Yasuyuki Hiraku
摘要： A semiconductor device includes a clock generating circuit and a jitter measurement circuit. The clock generating circuit is input with a control value for changing a cycle of the clock thereof. The jitter measurement circuit has a first logic circuit operated with using an output clock of the clock generating circuit as an input and a first delay element, and is configured to output the presence/absence of a jitter of the clock generating circuit.
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公开(公告)号：US10476511B2
公开(公告)日：2019-11-12
申请号：US16250414
申请日：2019-01-17
发明人： Yasuyuki Hiraku
摘要： A PLL circuit includes a phase comparator, first and second charge pumps, a filter generating a first control voltage from a current of the first charge pump, a comparator comparing a voltage of a first node with a reference voltage, a switch section outputting the reference voltage to the first node and outputting a current of the second charge pump to a second node in a high-speed lock mode, and outputting the current of the second charge pump to the first node and outputting a result from the comparator to the second node in a normal lock mode, a second filter generating a second control voltage by integrating a current of the first node, a third filter generating a third control voltage by integrating a current of the second node, and a voltage controlled oscillator generating a clock signal of a frequency corresponding to the first to third control voltages.
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公开(公告)号：US09819351B2
公开(公告)日：2017-11-14
申请号：US15431843
申请日：2017-02-14
发明人： Yasuyuki Hiraku
CPC分类号： H03L7/095 , H03L7/0891 , H03L7/091 , H03L7/093 , H03L7/107 , H03L7/1075 , H03L7/18 , H03L7/183 , H03L7/185
摘要： A PLL circuit having a desired performance is provided. A PLL circuit (100) includes a phase comparator (11) that detects a phase difference; a voltage control oscillator (12) that generates a signal to be returned to the phase comparator (11); and a loop filter (10) that is disposed between the phase comparator (11) and the voltage control oscillator (12) and includes an adder (50) that adds outputs from a proportional path (20), a first integral path (40), and a second integral path (30). The second integral path (30) and the first integral path (40) each include a cumulative adder, a ΔΣ modulator, and an RC filter. The lock detector (36) detects a lock state, controls a gain of the first cumulative adder (42) and a bandwidth of the first RC filter (45), and switches an input to a second ΔΣ modulator (33) to a fixed value.
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公开(公告)号：US09608646B2
公开(公告)日：2017-03-28
申请号：US15178775
申请日：2016-06-10
发明人： Yasuyuki Hiraku
CPC分类号： H03L7/095 , H03L7/0891 , H03L7/091 , H03L7/093 , H03L7/107 , H03L7/1075 , H03L7/18 , H03L7/183 , H03L7/185
摘要： A PLL circuit having a desired performance is provided. A PLL circuit (100) includes a phase comparator (11) that detects a phase difference; a voltage control oscillator (12) that generates a signal to be returned to the phase comparator (11); and a loop filter (10) that is disposed between the phase comparator (11) and the voltage control oscillator (12) and includes an adder (50) that adds outputs from a proportional path (20), a first integral path (40), and a second integral path (30). The second integral path (30) and the first integral path (40) each include a cumulative adder, a ΔΣ modulator, and an RC filter. The lock detector (36) detects a lock state, controls a gain of the first cumulative adder (42) and a bandwidth of the first RC filter (45), and switches an input to a second ΔΣ modulator (33) to a fixed value.
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