公开(公告)号：US20150270392A1

公开(公告)日：2015-09-24

申请号：US14733566

申请日：2015-06-08

Applicant: Renesas Electronics Corporation

Inventor： Yuki FUKUI ,  Hiroaki Katou

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7788 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813

Abstract: A method for manufacturing a semiconductor device, includes forming a recess over a surface of an n-type semiconductor substrate, forming a gate insulation film over an inner wall and a bottom face of the recess, embedding a gate electrode into the recess, forming a p-type base layer in a surface layer of the semiconductor substrate so as to be shallower than the recess, and forming an n-type source layer in the p-type base layer so as to be shallower than the p-type base layer. An impurity profile of the p-type base layer in a thickness direction includes a first peak, a second peak being located closer to a bottom face side of the semiconductor substrate than the first peak and being higher than the first peak, and a third peak located between the first peak and the second peak by implanting impurity ions three times or more at ion implantation energies different from each other in the forming of the p-type base layer.

Abstract translation: 一种半导体器件的制造方法，包括在n型半导体衬底的表面上形成凹部，在所述凹部的内壁和底面上形成栅极绝缘膜，将栅极电极嵌入到所述凹部中，形成 在半导体衬底的表面层中形成p型基底层，使其比凹槽浅，并且在p型基底层中形成比p型基底层浅的n型源极层。 p型基底层的厚度方向的杂质分布包括第一峰，位于比第一峰更靠近半导体衬底的底面的第二峰，高于第一峰，第三峰 通过在形成p型基底层时彼此不同的离子注入能量下注入杂质离子三次以上，位于第一峰值和第二峰值之间。

公开(公告)号：US20150079745A1

公开(公告)日：2015-03-19

申请号：US14552954

申请日：2014-11-25

Applicant: Renesas Electronics Corporation

Inventor： Yuki FUKUI ,  Hiroaki KATOU

IPC: H01L21/324 ,  H01L29/66

CPC classification number: H01L21/324 ,  H01L21/823487 ,  H01L23/4824 ,  H01L27/0922 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7813 ,  H01L29/7815 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring.

Abstract translation: 限制垂直晶体管的性质变化的产生。 在半导体衬底中形成垂直MOS晶体管。 第一层间电介质膜和第一源极布线形成在基板的前表面上。 第一源极布线形成在第一层间电介质膜上，并且与俯视图中的垂直MOS晶体管重叠。 触点被埋在第一层间绝缘膜中。 通过该触点，垂直MOS晶体管的n型源极层与第一源极配线连接。 开口在第一个源极接线中。

公开(公告)号：US20140187005A1

公开(公告)日：2014-07-03

申请号：US14196986

申请日：2014-03-04

Applicant: Renesas Electronics Corporation

Inventor： Yuki FUKUI ,  Hiroaki Katou

IPC: H01L29/778

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7788 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813

Abstract: A method for manufacturing a semiconductor device includes forming a recess over a surface of an n-type semiconductor substrate, forming a gate insulation film over an inner wall and a bottom face of the recess, embedding a gate electrode into the recess, forming a p-type base layer in the surface layer of the substrate so as to be shallower than the recess; and forming an n-type source layer in the p-type base layer so as to be shallower than the p-type base layer. The impurity profile of the p-type base layer in a thickness direction includes a second peak being located closer to a bottom face side of the substrate than the first peak and being higher than the first peak, and a third peak located between the first peak and the second peak by implanting impurity ions three times or more at ion implantation energies different from each other.

Abstract translation: 一种制造半导体器件的方法包括在n型半导体衬底的表面上形成凹陷，在凹槽的内壁和底面上形成栅极绝缘膜，将栅电极嵌入到凹部中，形成p 型基底层，以比该凹槽浅; 在p型基底层中形成n型源极层，使其比p型基底层浅。 p型基底层在厚度方向上的杂质分布包括第二峰位于比第一峰更靠近衬底的底面侧并高于第一峰，第三峰位于第一峰 并且通过在彼此不同的离子注入能量下注入杂质离子三次或更多的第二峰。