公开(公告)号：US20040145017A1

公开(公告)日：2004-07-29

申请号：US10757407

申请日：2004-01-15

Applicant: Renesas Technology Corp.

Inventor： Yuuichi Hirano ,  Shigenobu Maeda ,  Shigeto Maegawa

IPC: H01L027/01

CPC classification number: H01L29/6653 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/41758 ,  H01L29/42384 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7836 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a manufacturing method thereof are obtained which can restrain increase of the parasitic capacitance generated between contact plugs of source/drain regions and a gate electrode while reducing the area of the source/drain regions. A channel region is formed under a gate electrode 1. A pair of source/drain regions 2 are formed to sandwich the channel region. The source/drain regions 2 have a first part 3a being adjacent to the channel region and a second part 3b formed to protrude in a channel width direction from the first part 3a so that a part of outer peripheries of the source/drain regions 2 extend away from the gate electrode 1 in a plan view. Contact plugs 4 are formed on the second part 3b for connecting the source/drain regions 2 to source/drain wirings.

公开(公告)号：US20040051151A1

公开(公告)日：2004-03-18

申请号：US10456548

申请日：2003-06-09

Applicant: Renesas Technology Corp.

Inventor： Hai Dang ,  Shigenobu Maeda ,  Takuji Matsumoto ,  Yuuichi Hirano

IPC: H01L029/76

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78621

Abstract: Provided is an MOS transistor capable of reducing gate overlap capacitance without decreasing the driving current of the MOS transistor. Specifically, a double-angle smile oxidation structure is obtainable by curving the side surface of a gate electrode (22) so as to widen upwardly, and thickening the edge portion of a gate oxide film (21) by re-oxidation. The impurity concentration of a source/drain layer under the double-angle smile oxidation structure (a region around point B) is set to the range of 4null1018 cmnull3null40%.

Abstract translation: 提供了能够减小栅极重叠电容而不降低MOS晶体管的驱动电流的MOS晶体管。 具体地说，通过使栅电极（22）的侧面弯曲以向上变宽，通过再氧化来增厚栅极氧化膜（21）的边缘部分，可获得双角度微笑氧化结构。 在双角度微笑氧化结构（点B附近的区域）处的源极/漏极层的杂质浓度被设定为4×10 18 cm -3±40％的范围。

公开(公告)号：US20040179410A1

公开(公告)日：2004-09-16

申请号：US10813038

申请日：2004-03-31

Applicant: Renesas Technology Corp.

Inventor： Yuuichi Hirano ,  Takashi Ipposhi

IPC: G11C011/34

CPC classification number: G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

Abstract: A semiconductor storage device with high soft-error immunity is obtained. A semiconductor storage device has SRAM memory cells. NMOS transistors (Q1, Q4) are driver transistors, NMOS transistors (Q3, Q6) are access transistors, and PMOS transistors (Q2, Q5) are load transistors. An NMOS transistor (Q7) is a transistor for adding a resistance. The NMOS transistor (Q7) has its gate connected to a power supply (1). The NMOS transistor (Q7) has one of its source and drain connected to a storage node (ND1) and the other connected to the gates of the NMOS transistor (Q4) and the PMOS transistor (Q5). The resistance between the source and drain of the NMOS transistor (Q7) can be adjusted with the gate length, the gate width, the source/drain impurity concentration, etc., which is, for example, about several tens of kilohms (knull).

Abstract translation: 获得具有高软误差抗扰度的半导体存储装置。 半导体存储装置具有SRAM存储单元。 NMOS晶体管（Q1，Q4）是驱动晶体管，NMOS晶体管（Q3，Q6）是存取晶体管，PMOS晶体管（Q2，Q5）是负载晶体管。 NMOS晶体管（Q7）是用于增加电阻的晶体管。 NMOS晶体管（Q7）的栅极连接到电源（1）。 NMOS晶体管（Q7）的源极和漏极之一连接到存储节点（ND1），另一个连接到NMOS晶体管（Q4）和PMOS晶体管（Q5）的栅极。 NMOS晶体管（Q7）的源极和漏极之间的电阻可以通过栅极长度，栅极宽度，源极/漏极杂质浓度等进行调整，例如约几十千赫兹（kOmega） 。

公开(公告)号：US20040232554A1

公开(公告)日：2004-11-25

申请号：US10793841

申请日：2004-03-08

Applicant: Renesas Technology Corp.

Inventor： Yuuichi Hirano ,  Shigenobu Maeda ,  Takuji Matsumoto ,  Takashi Ipposhi ,  Shigeto Maegawa

IPC: H01L027/01

CPC classification number: H01L23/481 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/78639 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A back metal (18) is formed on an under surface (back surface) of the support substrate (10) and said back metal (18) is connected with the wiring (17a) through a heat radiating plug (16). The contact plug (15a), the heat radiating plug (16) the wiring (17a) and the back metal (18) is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film (11) and the support substrate (10).

Abstract translation: 半导体器件具有通过支撑衬底（10）上的氧化硅膜（11）形成的硅层（SOI层）（12）。 在SOI层（12）中形成晶体管（T1）。 布线（17a）通过接触插塞（15a）与晶体管（T1）的源极连接。 背衬金属（18）形成在支撑基板（10）的下表面（背面）上，背面金属（18）通过散热塞（16）与布线17a连接。 接触插头（15a），散热塞（16），布线（17a）和背金属（18）由诸如铝，钨等的金属制成，其具有比硅的热导率更高的导热性 氧化膜（11）和支撑基板（10）。

公开(公告)号：US20040227185A1

公开(公告)日：2004-11-18

申请号：US10754539

申请日：2004-01-12

Applicant: Renesas Technology Corp.

Inventor： Takuji Matsumoto ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

IPC: H01L027/01

CPC classification number: H01L29/66545 ,  H01L21/28052 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7845

Abstract: A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.

Abstract translation: 提供一种半导体器件及其制造方法，其可以适当地避免隔离击穿电压的降低，而不会引起诸如结电容增加的不利影响。 在通过形成凹部（14）使硅层（3）变薄之后形成杂质导入区域（11）。 因此，在位于元件隔离绝缘膜（5）的底部和BOX层（2）的上表面之间的p型硅层（3）的部分中不会注入n型杂质，避免了还原 的隔离击穿电压。 此外，由于杂质引入区域（11）形成为到达BOX层（2）的上表面，所以源极/漏极区域（12）的结电容不增加。

公开(公告)号：US20040026762A1

公开(公告)日：2004-02-12

申请号：US10459614

申请日：2003-06-12

Applicant: Renesas Technology Corp.

Inventor： Yuuichi Hirano ,  Takuji Matsumoto ,  Takashi Ipposhi

IPC: H01L029/76 ,  H01L031/062

CPC classification number: H01L28/20 ,  H01L27/0629

Abstract: It is an object to provide a semiconductor device in which a resistance value of a resistor formed by a silicon film is changed with difficulty. A resistor (31) is formed by an amorphous silicon film, and silicides (32a) and (32b) are formed in connecting portions of contact plugs (5a) and (5b) in a surface portion thereof. Since the resistor (31) is the amorphous silicon, a hydrogen atom is bonded with more difficulty as compared with the case in which polycrystalline silicon is used for a material of the resistor. Thus, it is possible to obtain a semiconductor device in which a resistance value of the resistor formed by the silicon film is changed with difficulty. Moreover, the suicides (32a) and (32b) are formed in the connecting portions of the contact plugs (5a) and (5b). Therefore, when contact holes for the contact plugs (5a) and (5b) are to be formed on a first interlayer insulating film (4a) by etching, the resistor (31) is etched with difficulty. Consequently, it is possible to obtain a semiconductor device in which the resistance value of the resistor (31) is changed with more difficulty.

Abstract translation: 本发明的目的是提供一种由硅膜形成的电阻器的电阻值难以改变的半导体器件。 电阻器（31）由非晶硅膜形成，并且在其接触插塞（5a）和（5b）的连接部分中形成硅化物（32a）和（32b）。 由于电阻器（31）是非晶硅，与将多晶硅用于电阻体材料的情况相比，氢原子更难以接合。 因此，可以获得其中由硅膜形成的电阻器的电阻值难以改变的半导体器件。 此外，在接触塞（5a）和（5b）的连接部分中形成自杀（32a）和（32b）。 因此，当通过蚀刻在第一层间绝缘膜（4a）上形成用于接触插头（5a）和（5b）的接触孔时，难以蚀刻电阻器（31）。 因此，可以获得其中电阻（31）的电阻值变得更难的半导体器件。