公开(公告)号：US20040232554A1

公开(公告)日：2004-11-25

申请号：US10793841

申请日：2004-03-08

Applicant: Renesas Technology Corp.

Inventor： Yuuichi Hirano ,  Shigenobu Maeda ,  Takuji Matsumoto ,  Takashi Ipposhi ,  Shigeto Maegawa

IPC: H01L027/01

CPC classification number: H01L23/481 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/78639 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A back metal (18) is formed on an under surface (back surface) of the support substrate (10) and said back metal (18) is connected with the wiring (17a) through a heat radiating plug (16). The contact plug (15a), the heat radiating plug (16) the wiring (17a) and the back metal (18) is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film (11) and the support substrate (10).

Abstract translation: 半导体器件具有通过支撑衬底（10）上的氧化硅膜（11）形成的硅层（SOI层）（12）。 在SOI层（12）中形成晶体管（T1）。 布线（17a）通过接触插塞（15a）与晶体管（T1）的源极连接。 背衬金属（18）形成在支撑基板（10）的下表面（背面）上，背面金属（18）通过散热塞（16）与布线17a连接。 接触插头（15a），散热塞（16），布线（17a）和背金属（18）由诸如铝，钨等的金属制成，其具有比硅的热导率更高的导热性 氧化膜（11）和支撑基板（10）。

公开(公告)号：US20040253458A1

公开(公告)日：2004-12-16

申请号：US10890108

申请日：2004-07-14

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Takuji Matsumoto ,  Toshiaki Iwamatsu

IPC: B32B009/04

CPC classification number: H01L21/3226 ,  H01L21/76251 ,  H01L21/76259 ,  H01L29/16 ,  Y10T428/265

Abstract: A semiconductor wafer includes an oxide film above a silicon layer, and a porous silicon layer which is located above the oxide film and serves as a gettering layer. Gettering of impurities from a silicon layer is not interrupted by the oxide film since the porous silicon layer is placed above the oxide film. The semiconductor wafer having the structure above can be produced by a bonding method. Bonding strength relative to the oxide film is ensured by placing a growth silicon layer between the oxide film and the porous silicon layer, compared with the case in which the oxide film and the porous silicon layer are directly bonded.

Abstract translation: 半导体晶片包括在硅层上方的氧化物膜和位于氧化物膜上方并用作吸杂层的多孔硅层。 由于多孔硅层位于氧化膜的上方，从硅层中除去杂质不会被氧化膜中断。 具有上述结构的半导体晶片可以通过接合方法制造。 与氧化膜和多孔硅层直接接合的情况相比，通过将生长硅层放置在氧化膜和多孔硅层之间来确保相对于氧化膜的结合强度。

公开(公告)号：US20040207017A1

公开(公告)日：2004-10-21

申请号：US10841469

申请日：2004-05-10

Applicant: Renesas Technology Corp.

Inventor： Takuji Matsumoto ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC: H01L029/76

CPC classification number: H01L29/78615 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1112 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  Y10S257/904

Abstract: It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through nullInull in a transverse direction (a vertical direction in the drawing), a central null-null functions as a gate electrode of an original MOS transistor.

公开(公告)号：US20040051151A1

公开(公告)日：2004-03-18

申请号：US10456548

申请日：2003-06-09

Applicant: Renesas Technology Corp.

Inventor： Hai Dang ,  Shigenobu Maeda ,  Takuji Matsumoto ,  Yuuichi Hirano

IPC: H01L029/76

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78621

Abstract: Provided is an MOS transistor capable of reducing gate overlap capacitance without decreasing the driving current of the MOS transistor. Specifically, a double-angle smile oxidation structure is obtainable by curving the side surface of a gate electrode (22) so as to widen upwardly, and thickening the edge portion of a gate oxide film (21) by re-oxidation. The impurity concentration of a source/drain layer under the double-angle smile oxidation structure (a region around point B) is set to the range of 4null1018 cmnull3null40%.

Abstract translation: 提供了能够减小栅极重叠电容而不降低MOS晶体管的驱动电流的MOS晶体管。 具体地说，通过使栅电极（22）的侧面弯曲以向上变宽，通过再氧化来增厚栅极氧化膜（21）的边缘部分，可获得双角度微笑氧化结构。 在双角度微笑氧化结构（点B附近的区域）处的源极/漏极层的杂质浓度被设定为4×10 18 cm -3±40％的范围。

公开(公告)号：US20040227185A1

公开(公告)日：2004-11-18

申请号：US10754539

申请日：2004-01-12

Applicant: Renesas Technology Corp.

Inventor： Takuji Matsumoto ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

IPC: H01L027/01

CPC classification number: H01L29/66545 ,  H01L21/28052 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7845

Abstract: A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.

Abstract translation: 提供一种半导体器件及其制造方法，其可以适当地避免隔离击穿电压的降低，而不会引起诸如结电容增加的不利影响。 在通过形成凹部（14）使硅层（3）变薄之后形成杂质导入区域（11）。 因此，在位于元件隔离绝缘膜（5）的底部和BOX层（2）的上表面之间的p型硅层（3）的部分中不会注入n型杂质，避免了还原 的隔离击穿电压。 此外，由于杂质引入区域（11）形成为到达BOX层（2）的上表面，所以源极/漏极区域（12）的结电容不增加。

公开(公告)号：US20040222465A1

公开(公告)日：2004-11-11

申请号：US10866701

申请日：2004-06-15

Applicant: Renesas Technology Corp.

Inventor： Takuji Matsumoto ,  Hirokazu Sayama ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Kazunobu Ota

IPC: H01L029/76 ,  H01L029/94

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/78615 ,  H01L29/78621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).

Abstract translation: 提供一种半导体器件，其通过降低寄生双极晶体管的增益来实现故障的减小和工作特性变化，及其制造方法。 在硅层（3）的上表面上部分地形成氧化硅膜（6）。 多晶硅的栅电极（7）部分地形成在氧化硅膜（6）上。 栅电极（7）下方的氧化硅膜（6）的一部分用作栅极绝缘膜。 在栅极（7）的每个侧表面上形成氮化硅膜（9），其间具有氧化硅膜（8）。 氧化硅膜（8）和氮化硅膜（9）形成在氧化硅膜（6）上。 氧化硅膜（8）在栅极长度方向上的宽度（W1）大于氧化硅膜（6）的厚度（T1）。

公开(公告)号：US20040075141A1

公开(公告)日：2004-04-22

申请号：US10459490

申请日：2003-06-12

Applicant: Renesas Technology Corp.

Inventor： Shigenobu Maeda ,  Shigeto Maegawa ,  Takuji Matsumoto

IPC: H01L027/01

CPC classification number: H01L29/045 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78654 ,  H01L29/78687 ,  H01L29/78696

Abstract: There is provided a semiconductor device which is formed on a semiconductor substrate and allows effective use of the feature of the semiconductor substrate, and there is also provided a method of manufacturing the same. An N-channel MOS transistor including a P-type body layer (3a), and a P-type active layer (6) for body voltage application which is in contact with the P-type body layer (3a) are formed on an SOI substrate which is formed to align a crystal direction of a support substrate (1) with a crystal direction of an SOI layer (3). A path connecting the P-type body layer (3a) and the P-type active layer (6) for body voltage application is aligned parallel to the crystal direction of the SOI layer (3). Since hole mobility is higher in the crystal direction, parasitic resistance (Ra, Rb) can be reduced in the above path. This speeds up voltage transmission to the P-type body layer (3a) and improves voltage fixing capability in the P-type body layer (3a).

Abstract translation: 提供一种半导体器件，其形成在半导体衬底上并且有效地利用了半导体衬底的特征，并且还提供了一种制造该半导体衬底的方法。 包括P型体层（3a）和与P型体层（3a）接触的体电压施加用P型有源层（6）的N沟道MOS晶体管形成在SOI 衬底，其被形成为使支撑衬底（1）的<110>晶体方向与SOI层（3）的<100>晶体方向对准。 连接P型体层（3a）和用于体电压施加的P型有源层（6）的路径平行于SOI层（3）的<100>晶体方向排列。 由于在<100>晶体方向的空穴迁移率较高，所以在上述路径中可以减小寄生电阻（Ra，Rb）。 这加快了P型体层（3a）的电压传输，提高了P型体层（3a）的电压固定能力。

公开(公告)号：US20040026762A1

公开(公告)日：2004-02-12

申请号：US10459614

申请日：2003-06-12

Applicant: Renesas Technology Corp.

Inventor： Yuuichi Hirano ,  Takuji Matsumoto ,  Takashi Ipposhi

IPC: H01L029/76 ,  H01L031/062

CPC classification number: H01L28/20 ,  H01L27/0629

Abstract: It is an object to provide a semiconductor device in which a resistance value of a resistor formed by a silicon film is changed with difficulty. A resistor (31) is formed by an amorphous silicon film, and silicides (32a) and (32b) are formed in connecting portions of contact plugs (5a) and (5b) in a surface portion thereof. Since the resistor (31) is the amorphous silicon, a hydrogen atom is bonded with more difficulty as compared with the case in which polycrystalline silicon is used for a material of the resistor. Thus, it is possible to obtain a semiconductor device in which a resistance value of the resistor formed by the silicon film is changed with difficulty. Moreover, the suicides (32a) and (32b) are formed in the connecting portions of the contact plugs (5a) and (5b). Therefore, when contact holes for the contact plugs (5a) and (5b) are to be formed on a first interlayer insulating film (4a) by etching, the resistor (31) is etched with difficulty. Consequently, it is possible to obtain a semiconductor device in which the resistance value of the resistor (31) is changed with more difficulty.

Abstract translation: 本发明的目的是提供一种由硅膜形成的电阻器的电阻值难以改变的半导体器件。 电阻器（31）由非晶硅膜形成，并且在其接触插塞（5a）和（5b）的连接部分中形成硅化物（32a）和（32b）。 由于电阻器（31）是非晶硅，与将多晶硅用于电阻体材料的情况相比，氢原子更难以接合。 因此，可以获得其中由硅膜形成的电阻器的电阻值难以改变的半导体器件。 此外，在接触塞（5a）和（5b）的连接部分中形成自杀（32a）和（32b）。 因此，当通过蚀刻在第一层间绝缘膜（4a）上形成用于接触插头（5a）和（5b）的接触孔时，难以蚀刻电阻器（31）。 因此，可以获得其中电阻（31）的电阻值变得更难的半导体器件。