公开(公告)号：US20040061200A1

公开(公告)日：2004-04-01

申请号：US10461352

申请日：2003-06-16

Applicant: Renesas Technology Corp.

Inventor： Toshiaki Iwamatsu ,  Shigenobu Maeda

IPC: H01L023/544

CPC classification number: H01L21/76243 ,  H01L21/02027 ,  H01L21/67092 ,  H01L21/68 ,  H01L21/76254 ,  H01L21/76256 ,  H01L23/544 ,  H01L29/045 ,  H01L29/78606 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer and its manufacturing method are provided where the current driving capability of a MOS transistor can be sufficiently enhanced. An SOI layer wafer in which an SOI layer (32) is formed has a crystal direction notch (32a) and a crystal direction notch (32b). The SOI layer wafer and a supporting substrate wafer (1) are bonded to each other in such a way that the notch (32a) and a crystal direction notch (1a) of the supporting substrate wafer (1) coincide with each other. When bonding the two wafers by using the notch (32a) and the notch (1a) to position the two wafers, the other notch (32b) of the SOI layer wafer can be engaged with a guide member of the semiconductor wafer manufacturing apparatus to prevent positioning error due to relative turn between the wafers. Thus an MOS transistor with a sufficiently improved current driving capability can be fabricated on the semiconductor wafer with the two wafers positioned in crystal directions shifted from each other.

Abstract translation: 提供一种可以充分提高MOS晶体管的电流驱动能力的半导体晶片及其制造方法。 其中形成SOI层（32）的SOI层晶片具有<100>晶体切口（32a）和<110>晶体方向凹口（32b）。 SOI层晶片和支撑基板晶片（1）以使得支撑基板晶片（1）的凹口（32a）和<110>晶体方向凹口（1a）彼此重合的方式彼此结合 。 当通过使用凹口（32a）和凹口（1a）将两个晶片接合以定位两个晶片时，SOI层晶片的另一个凹口（32b）可以与半导体晶片制造设备的引导构件接合，以防止 由于晶片之间的相对转动导致的定位误差。 因此，可以在半导体晶片上制造具有充分改善的电流驱动能力的MOS晶体管，其中两个晶片位于晶体方向彼此偏移。

公开(公告)号：US20040222465A1

公开(公告)日：2004-11-11

申请号：US10866701

申请日：2004-06-15

Applicant: Renesas Technology Corp.

Inventor： Takuji Matsumoto ,  Hirokazu Sayama ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Kazunobu Ota

IPC: H01L029/76 ,  H01L029/94

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/78615 ,  H01L29/78621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).

Abstract translation: 提供一种半导体器件，其通过降低寄生双极晶体管的增益来实现故障的减小和工作特性变化，及其制造方法。 在硅层（3）的上表面上部分地形成氧化硅膜（6）。 多晶硅的栅电极（7）部分地形成在氧化硅膜（6）上。 栅电极（7）下方的氧化硅膜（6）的一部分用作栅极绝缘膜。 在栅极（7）的每个侧表面上形成氮化硅膜（9），其间具有氧化硅膜（8）。 氧化硅膜（8）和氮化硅膜（9）形成在氧化硅膜（6）上。 氧化硅膜（8）在栅极长度方向上的宽度（W1）大于氧化硅膜（6）的厚度（T1）。

公开(公告)号：US20040075141A1

公开(公告)日：2004-04-22

申请号：US10459490

申请日：2003-06-12

Applicant: Renesas Technology Corp.

Inventor： Shigenobu Maeda ,  Shigeto Maegawa ,  Takuji Matsumoto

IPC: H01L027/01

CPC classification number: H01L29/045 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78654 ,  H01L29/78687 ,  H01L29/78696

Abstract: There is provided a semiconductor device which is formed on a semiconductor substrate and allows effective use of the feature of the semiconductor substrate, and there is also provided a method of manufacturing the same. An N-channel MOS transistor including a P-type body layer (3a), and a P-type active layer (6) for body voltage application which is in contact with the P-type body layer (3a) are formed on an SOI substrate which is formed to align a crystal direction of a support substrate (1) with a crystal direction of an SOI layer (3). A path connecting the P-type body layer (3a) and the P-type active layer (6) for body voltage application is aligned parallel to the crystal direction of the SOI layer (3). Since hole mobility is higher in the crystal direction, parasitic resistance (Ra, Rb) can be reduced in the above path. This speeds up voltage transmission to the P-type body layer (3a) and improves voltage fixing capability in the P-type body layer (3a).

Abstract translation: 提供一种半导体器件，其形成在半导体衬底上并且有效地利用了半导体衬底的特征，并且还提供了一种制造该半导体衬底的方法。 包括P型体层（3a）和与P型体层（3a）接触的体电压施加用P型有源层（6）的N沟道MOS晶体管形成在SOI 衬底，其被形成为使支撑衬底（1）的<110>晶体方向与SOI层（3）的<100>晶体方向对准。 连接P型体层（3a）和用于体电压施加的P型有源层（6）的路径平行于SOI层（3）的<100>晶体方向排列。 由于在<100>晶体方向的空穴迁移率较高，所以在上述路径中可以减小寄生电阻（Ra，Rb）。 这加快了P型体层（3a）的电压传输，提高了P型体层（3a）的电压固定能力。

公开(公告)号：US20040207017A1

公开(公告)日：2004-10-21

申请号：US10841469

申请日：2004-05-10

Applicant: Renesas Technology Corp.

Inventor： Takuji Matsumoto ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC: H01L029/76

CPC classification number: H01L29/78615 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1112 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  Y10S257/904

Abstract: It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through nullInull in a transverse direction (a vertical direction in the drawing), a central null-null functions as a gate electrode of an original MOS transistor.

公开(公告)号：US20040145017A1

公开(公告)日：2004-07-29

申请号：US10757407

申请日：2004-01-15

Applicant: Renesas Technology Corp.

Inventor： Yuuichi Hirano ,  Shigenobu Maeda ,  Shigeto Maegawa

IPC: H01L027/01

CPC classification number: H01L29/6653 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/41758 ,  H01L29/42384 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7836 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a manufacturing method thereof are obtained which can restrain increase of the parasitic capacitance generated between contact plugs of source/drain regions and a gate electrode while reducing the area of the source/drain regions. A channel region is formed under a gate electrode 1. A pair of source/drain regions 2 are formed to sandwich the channel region. The source/drain regions 2 have a first part 3a being adjacent to the channel region and a second part 3b formed to protrude in a channel width direction from the first part 3a so that a part of outer peripheries of the source/drain regions 2 extend away from the gate electrode 1 in a plan view. Contact plugs 4 are formed on the second part 3b for connecting the source/drain regions 2 to source/drain wirings.

公开(公告)号：US20040051151A1

公开(公告)日：2004-03-18

申请号：US10456548

申请日：2003-06-09

Applicant: Renesas Technology Corp.

Inventor： Hai Dang ,  Shigenobu Maeda ,  Takuji Matsumoto ,  Yuuichi Hirano

IPC: H01L029/76

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78621

Abstract: Provided is an MOS transistor capable of reducing gate overlap capacitance without decreasing the driving current of the MOS transistor. Specifically, a double-angle smile oxidation structure is obtainable by curving the side surface of a gate electrode (22) so as to widen upwardly, and thickening the edge portion of a gate oxide film (21) by re-oxidation. The impurity concentration of a source/drain layer under the double-angle smile oxidation structure (a region around point B) is set to the range of 4null1018 cmnull3null40%.

Abstract translation: 提供了能够减小栅极重叠电容而不降低MOS晶体管的驱动电流的MOS晶体管。 具体地说，通过使栅电极（22）的侧面弯曲以向上变宽，通过再氧化来增厚栅极氧化膜（21）的边缘部分，可获得双角度微笑氧化结构。 在双角度微笑氧化结构（点B附近的区域）处的源极/漏极层的杂质浓度被设定为4×10 18 cm -3±40％的范围。

公开(公告)号：US20040232554A1

公开(公告)日：2004-11-25

申请号：US10793841

申请日：2004-03-08

Applicant: Renesas Technology Corp.

Inventor： Yuuichi Hirano ,  Shigenobu Maeda ,  Takuji Matsumoto ,  Takashi Ipposhi ,  Shigeto Maegawa

IPC: H01L027/01

CPC classification number: H01L23/481 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/78639 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A back metal (18) is formed on an under surface (back surface) of the support substrate (10) and said back metal (18) is connected with the wiring (17a) through a heat radiating plug (16). The contact plug (15a), the heat radiating plug (16) the wiring (17a) and the back metal (18) is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film (11) and the support substrate (10).

Abstract translation: 半导体器件具有通过支撑衬底（10）上的氧化硅膜（11）形成的硅层（SOI层）（12）。 在SOI层（12）中形成晶体管（T1）。 布线（17a）通过接触插塞（15a）与晶体管（T1）的源极连接。 背衬金属（18）形成在支撑基板（10）的下表面（背面）上，背面金属（18）通过散热塞（16）与布线17a连接。 接触插头（15a），散热塞（16），布线（17a）和背金属（18）由诸如铝，钨等的金属制成，其具有比硅的热导率更高的导热性 氧化膜（11）和支撑基板（10）。

公开(公告)号：US20040150047A1

公开(公告)日：2004-08-05

申请号：US10748273

申请日：2003-12-31

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC: H01L021/84 ,  H01L031/0392

CPC classification number: H01L29/78615 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an Nnull block region in an Nnull block resist film prevents a well region located under the gate-directional extension region from implantation of an N-type impurity. A high resistance forming region, which is the well region having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode , can be formed as a high resistance forming region narrower than a conventional high resistance forming region . Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

Abstract translation: 在形成NMOS晶体管的源极/漏极区域的情况下，N +块阻挡膜51中的N +块区域41的栅极延伸区域<41a> 11'，其从N型杂质的注入位于栅极方向延伸区域41a之下。 可以形成具有在栅电极9的纵向延伸上注入N型杂质的可能性的具有高电阻形成区域的高电阻形成区域， 比传统的高电阻形成区域。 因此，获得具有能够降低体电阻的部分隔离体固定的SOI结构的半导体器件及其制造方法。