-
1.发明授权
公开(公告)号：US4460959A
公开(公告)日：1984-07-17
申请号：US302904
申请日：1981-09-16
CPC分类号： G06F12/0859
摘要： A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.
摘要翻译： 公开了一种由高速缓冲存储器系统和传送控制逻辑单元组成的逻辑控制系统，用于将来自中央存储器系统的程序信息和CPU（中央处理单元）指令的流程从公共通信总线上的CPU接收到CPU。 CPU和传输控制逻辑单元通过具有公共通信总线的高速缓冲存储器系统进行通信。 响应于对中央存储器系统的CPU请求，传输控制逻辑单元从高速缓冲存储器系统请求程序信息和指令，并以这样的方式呈现给CPU，以避免由信息传输延迟引起的CPU活动中断 。
-
公开(公告)号：US4451883A
公开(公告)日：1984-05-29
申请号：US326260
申请日：1981-12-01
CPC分类号： G06F9/30032 , G06F9/30167
摘要： A data processing system includes a memory subsystem for storing operands and instructions and a central processing unit (CPU) for manipulating the operands by executing the instructions. The CPU includes a control store for generating signals for controlling the CPU operation. Shifters made up of multiplexers shift operands between an outer bus and a write bus in response to control store signals. The multiplexers shift the operands left or right 1, 2 or 4-bit positions including open shifts and circular shifts and also perform byte position shifting and twinning.
摘要翻译： 数据处理系统包括用于存储操作数和指令的存储器子系统和用于通过执行指令来操纵操作数的中央处理单元（CPU）。 CPU包括用于产生用于控制CPU操作的信号的控制存储器。 由复用器组成的移位器响应于控制存储信号在外部总线和写入总线之间移动操作数。 多路复用器将操作数向左或向右移位1,2或4位位置，包括开位移和循环移位，并且还执行字节位移和孪生。
-
公开(公告)号：US4467416A
公开(公告)日：1984-08-21
申请号：US302898
申请日：1981-09-16
CPC分类号： G06F9/325 , G06F9/3016
摘要： A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.
摘要翻译： 公开了一种逻辑控制系统，用于将过程信息和CPU（中央处理单元）指令的流程从中央存储器系统适应到CPU，而不会因为传输延迟或定时方差而危及存储器带宽或CPU执行速度。 在指令执行期间容纳指令修改和多任务分配。
-
公开(公告)号：US4455606A
公开(公告)日：1984-06-19
申请号：US302902
申请日：1981-09-16
CPC分类号： G06F13/4234 , G06F13/16
摘要： This disclosure relates to a control system for transferring binary words from a memory system. One thirty two bit double word may be loaded into a selected two of four sixteen bit registers. As a first of the two selected registers is read, another thirty two bit word may be loaded into the unselected registers. Alternatively, sixteen bit single words may be loaded into and read from the registers. When a word has procedural information, it is read from the registers onto a CPU control bus via a multiplexer. When a word is an encoded computer instruction to the CPU, it is read from the registers into a logic unit via a multiplexer. A decoded instruction from the logic unit is read onto a CPU control bus.
摘要翻译： 本公开涉及一种用于从存储器系统传送二进制字的控制系统。 一个三十二位双字可能被加载到四个16位寄存器中选定的两个。 由于读取了两个选定的寄存器中的第一个，可以将另外三十二位的位加载到未选择的寄存器中。 或者，可以将16位单个字加载到寄存器中并从寄存器读取。 当一个单词具有程序信息时，它通过多路复用器从寄存器读取到CPU控制总线上。 当一个字为CPU的编码计算机指令时，它通过多路复用器从寄存器读入逻辑单元。 来自逻辑单元的解码指令被读取到CPU控制总线上。
-
公开(公告)号：US4467417A
公开(公告)日：1984-08-21
申请号：US302903
申请日：1981-09-16
CPC分类号： G06F9/30181 , G06F9/3016 , G06F9/325
摘要： A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.
摘要翻译： 公开了一种逻辑控制系统，用于将过程信息和CPU（中央处理单元）指令的流程从中央存储器系统适应到CPU，而不会因为传输延迟或定时方差而危及存储器带宽或CPU执行速度。 在指令执行期间容纳指令修改和多任务分配。
-
6.发明授权
公开(公告)号：US4349874A
公开(公告)日：1982-09-14
申请号：US140630
申请日：1980-04-15
CPC分类号： G06F12/0862 , G06F2212/6022
摘要： In a data processing system, a central processor unit requests procedural data words or non-procedural data words stored in the system memory. A control store device executes firmware instructions including a local bus field for controlling the transfer of the requested procedural data words and non-procedural data words to the central processor unit. The requested procedural data words and non-procedural data words are transferred to the central processing unit by an interfacing device including a data bus latch for receiving the procedural data words and non-procedural data words transferred from the memory, a prefetch buffer for storing up to four words, a first set of OR gate circuits for selectively transferring the procedural data words stored in the prefetch buffer to a procedural data multiplexer for assembling either a procedural data word or a procedure address, and a second set of OR gate circuits for selectively transferring either a procedural data word or non-procedural data word to the source bus or a procedural data address or non-procedural data address to the source bus for transfer to the central processor unit.
摘要翻译： 在数据处理系统中，中央处理器单元请求存储在系统存储器中的过程数据字或非程序数据字。 控制存储设备执行固件指令，其包括本地总线字段，用于控制所请求的过程数据字和非程序数据字向中央处理器单元的传送。 所请求的程序数据字和非程序数据字通过包括用于接收程序数据字的数据总线锁存器和从存储器传送的非程序数据字的接口装置传送到中央处理器，用于存储的预取缓冲器 四个字，第一组OR门电路，用于选择性地将存储在预取缓冲器中的程序数据字传送到程序数据多路复用器，用于组装程序数据字或程序地址，以及第二组OR门电路，用于选择性地 将程序数据字或非程序数据字传送到源总线或程序数据地址或非程序数据地址到源总线以传送到中央处理器单元。
-
公开(公告)号：US4472773A
公开(公告)日：1984-09-18
申请号：US302897
申请日：1981-09-16
CPC分类号： G06F9/30
摘要： A decoding logic system in a logic control system of a data processing system is disclosed, wherein the data processing system is comprized of a main memory unit communicating with the logic control system by way of a common communication bus, and wherein the logic control system and a CPU (central processing unit) communicate by way of a local communication bus. In response to a CPU request, CPU instructions stored in the main memory unit are received by the logic decoding system, and presented to the CPU in such a manner as to accommodate both memory bit and CPU computed bit modifications to the instructions during instruction execution, while avoiding interruptions in CPU activity caused by information transfer delays internal to the logic decoding system. Instruction modification also may be effected by incrementing or decrementing the instructions under firmware control.
摘要翻译： 公开了一种数据处理系统的逻辑控制系统中的解码逻辑系统，其中数据处理系统由与公共通信总线与逻辑控制系统通信的主存储单元组成，其中逻辑控制系统和 CPU（中央处理单元）通过本地通信总线进行通信。 响应于CPU请求，存储在主存储器单元中的CPU指令由逻辑解码系统接收，并且以在指令执行期间容纳存储器位和CPU计算的位修改的方式呈现给CPU， 同时避免在逻辑解码系统内部的信息传输延迟引起的CPU活动中断。 也可以通过在固件控制下增加或减少指令来实现指令修改。
-
8.发明授权
公开(公告)号：US4206503A
公开(公告)日：1980-06-03
申请号：US868251
申请日：1978-01-10
CPC分类号： G06F9/342
摘要： A final effective address of an operand is generated in a microprogrammed data processing system by use of a base address register which may include an unindexed address, an index register which may include an indexed address value, an instruction register which may include an instruction word, which instruction word provides control over the addressing of a control store dependent upon the state of a selected one of a plurality of test conditions. One of the test conditions indicating whether some of the addressing values used in the generation of the effective address are in a short address format or in a long address format. The address control store word provides signals for controlling the operation of the system, including the branch in between such major operations as instruction fetching, addressing, reading, writing, and execution as well as branching between minor operations which are included in the major operations.
摘要翻译： 操作数的最终有效地址是通过使用可包括无索引地址的基址寄存器，可包括索引地址值的索引寄存器，可包括指令字的指令寄存器，在微程序数据处理系统中生成的， 该指令字取决于多个测试条件中所选择的一个的状态来提供对控制存储器的寻址的控制。 测试条件之一是指示在生成有效地址时使用的一些寻址值是短地址格式还是长地址格式。 地址控制存储字提供用于控制系统的操作的信号，包括在诸如指令获取，寻址，读取，写入和执行等主要操作之间的分支以及主要操作中包括的次要操作之间的分支。
-
公开(公告)号：US5983012A
公开(公告)日：1999-11-09
申请号：US128456
申请日：1993-09-28
申请人： Richard S. Bianchi , Dennis R. Flynn , Marcia T. Fogelgren , Richard A. Lemay , Mary E. Tovell , William E. Woods
发明人： Richard S. Bianchi , Dennis R. Flynn , Marcia T. Fogelgren , Richard A. Lemay , Mary E. Tovell , William E. Woods
CPC分类号： G06F21/31 , G06F13/10 , G06F13/105 , G06F21/6281 , G06F9/45537 , G06F2221/2105
摘要： An emulator executes on a second data processing system as a second system user level process including a first system user level program, a first system executive program, and first system user and executive tasks. An emulator level is interposed between the second system user level process and a kernel level and contains pseudo device drivers. Each pseudo device driver corresponds to a first system input/output device. The kernel level includes kernel processes, each kernel process corresponding to a pseudo device driver. The second system hardware platform includes a plurality of second system input/output devices, wherein each second system input output device corresponds to a kernel process. Each combination of a pseudo device driver, a corresponding kernel process and a corresponding second system input/output device executes in a second system process and emulates the operations of a corresponding first system input/output task and the corresponding first system input/output device. The pseudo device drivers are constructed of a plurality of pseudo device queues, a return queue and a queue manager.
摘要翻译： 模拟器在第二数据处理系统上执行，作为包括第一系统用户级程序，第一系统执行程序以及第一系统用户和执行任务的第二系统用户级进程。 在第二系统用户级别进程和内核级别之间插入一个仿真器级别，并包含伪设备驱动程序。 每个伪设备驱动程序对应于第一系统输入/输出设备。 内核级别包括内核进程，每个内核进程对应一个伪设备驱动程序。 第二系统硬件平台包括多个第二系统输入/输出设备，其中每个第二系统输入输出设备对应于内核进程。 伪设备驱动器，相应的内核进程和对应的第二系统输入/输出设备的每个组合在第二系统进程中执行并且模拟对应的第一系统输入/输出任务和对应的第一系统输入/输出设备的操作。 伪设备驱动程序由多个伪设备队列，返回队列和队列管理器构成。
-
10.发明授权
公开(公告)号：US5136500A
公开(公告)日：1992-08-04
申请号：US366225
申请日：1989-06-12
IPC分类号： G06F13/16 , G06F15/167
CPC分类号： G06F15/167 , G06F13/1663
摘要： A memory controller in which a number of local memories are primarily dedicated to the shared use of a number of local processors of a data processing system to increase the efficiency of use of both the processors and memories. A controller is associated with each local memory to control connection of any one of the local processors to its associated local memory. A local processor can also be connected via a controller and an adapter circuit connected to the controller to a system bus to obtain access to circuits connected thereto. In addition, a system processor connected to the system bus may also be connected to any particular one of the local memories via its associated controller and adapter connected thereto to load data or programs into the local memory for use by the local processors, and to read out the results of previous processing done by the local processors.
-
-
-
-
-
-
-
-
-
搜索结果
44 条记录 (耗时 0.025 秒)
