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1.发明授权Method for organizing state machine by selectively grouping status signals as inputs and classifying commands to be executed into performance sensitive and nonsensitive categories 失效通过选择性地将状态信号分组为输入并将待执行的命令分类为性能敏感和非敏感类别来组织状态机的方法
公开(公告)号：US5375248A
公开(公告)日：1994-12-20
申请号：US99117
申请日：1993-07-29
摘要： A virtual memory unit (VMU) includes a state machine for controlling its operations in response to commands received from another unit. The state machine includes a plurality of programmable array logic (PAL) devices which are connected to gather status from the different sections of the unit. The outputs of the PAL devices connect in common and supply a first address input to an addressable state memory. The state memory includes a plurality of locations, each of which stores a binary code defining a different machine state. The state memory locations are accessed as a function of the status signals and current state and used in turn to generate the required subcommands for executing the received commands. The state machine makes it possible to easily classify the received commands to their complexity and urgency in terms of their effect on overall system performance.
摘要翻译： 虚拟存储器单元（VMU）包括用于响应于从另一单元接收的命令来控制其操作的状态机。 状态机包括多个可编程阵列逻辑（PAL）装置，其被连接以从该装置的不同部分收集状态。 PAL设备的输出共同连接，并将第一地址输入提供给可寻址状态存储器。 状态存储器包括多个位置，每个位置存储限定不同机器状态的二进制代码。 根据状态信号和当前状态访问状态存储器位置，并依次使用生成用于执行接收到的命令的必需子命令。 状态机使得可以在接收到的命令的整体系统性能方面对其复杂性和紧迫性进行分类。
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2.发明授权Buffered address stack register with parallel input registers and overflow protection 失效缓冲地址堆栈寄存器具有并行输入寄存器和溢出保护
公开(公告)号：US5161217A
公开(公告)日：1992-11-03
申请号：US418084
申请日：1989-10-06
IPC分类号： G06F7/78
CPC分类号： G06F7/78
摘要： A last-in, first-out register having multiple address input ports and capable of storing a plurality of addresses. Address loading operations are over-lapped with address reading operations to speed up the rate at which addresses may be stored in and retrieved from the register. When the register is full of addresses it provides an indication which permits: the addresses already stored in the register to be read out and stored in an external memory, then additional addresses to be stored in the register, and subsequently the addresses transferred to the memory for storage to be retransferred to the buffer address register for read out.
摘要翻译： 一个具有多个地址输入端口并且能够存储多个地址的先进先出寄存器。 地址加载操作与地址读取操作重叠，以加快地址可以从寄存器存储和检索的速率。 当寄存器充满地址时，它提供一个指示，允许：已经存储在寄存器中的地址被读出并存储在外部存储器中，然后存储在寄存器中的附加地址，以及随后传送到存储器的地址 用于存储重新发送到缓冲地址寄存器以进行读出。
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公开(公告)号：US4837738A
公开(公告)日：1989-06-06
申请号：US927631
申请日：1986-11-05
IPC分类号： G06F12/04
CPC分类号： G06F12/04
摘要： An address boundary detector is disclosed that functions with an arithmetic logic unit (ALU) in a computer processor while the ALU generates addresses by adding an offset or displacement to a base address. The detector monitors bits of addresses to determine whether a data item can be completely stored within the same block or page of memory as that addressed by the base address from which it was derived.
摘要翻译： 公开了一种地址边界检测器，其在计算机处理器中与算术逻辑单元（ALU）一起工作，而ALU通过向基址添加偏移或位移来生成地址。 检测器监视地址位，以确定数据项是否可以完全存储在与从其导出的基址所寻址的存储器相同的块或页内。
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4.发明授权State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections 失效用于通过根据从不同功能部分接收的状态信号来容纳不可见的时间依赖来在最小数量的周期内执行命令的状态机
公开(公告)号：US5280595A
公开(公告)日：1994-01-18
申请号：US593923
申请日：1990-10-05
摘要： A virtual memory unit (VMU) includes a state machine for controlling its operations in response to commands received from another unit. The state machine includes a plurality of programmable array logic (PAL) devices which are connected to gather status from the different sections of the unit. The outputs of the PAL devices connect in common and supply a first address input to an addressable state memory. The state memory includes a plurality of locations, each of which stores a binary code defining a different machine state. The state memory locations are accessed as a function of the status signals and current state and used in turn to generate the required subcommands for executing the received commands. The state machine makes it possible to easily classify the received commands to their complexity and urgency in terms of their effect on overall system performance.
摘要翻译： 虚拟存储器单元（VMU）包括用于响应于从另一单元接收的命令来控制其操作的状态机。 状态机包括多个可编程阵列逻辑（PAL）装置，其被连接以从该装置的不同部分收集状态。 PAL设备的输出共同连接，并将第一地址输入提供给可寻址状态存储器。 状态存储器包括多个位置，每个位置存储限定不同机器状态的二进制代码。 根据状态信号和当前状态访问状态存储器位置，并依次使用生成用于执行接收到的命令的必需子命令。 状态机使得可以在接收到的命令的整体系统性能方面对其复杂性和紧迫性进行分类。
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公开(公告)号：US5243601A
公开(公告)日：1993-09-07
申请号：US593411
申请日：1990-10-05
申请人： Steven A. Tague , William E. Woods
发明人： Steven A. Tague , William E. Woods
CPC分类号： G06F11/28 , G06F11/0721 , G06F11/0751 , G06F11/0793 , G06F11/0763 , G06F2201/86 , G06F2201/865
摘要： A method and apparatus pertaining to a firmware control unit for detecting when such control unit is not behaving properly. The control unit is organized to include in each location of the unit's control store, to which control is not expected to transfer, a predetermined type of pattern containing an address specifying the address of that location, a suitable tag identifying the probable reason for the unexplained jump, and a transfer of control to the appropriate entry point in a reporting firmware routine within the control store. The reporting firmware routine has a number of entry points for collecting all the executions of unexpected locations and for storing the appropriate address and tag information in a predetermined register file for later referencing by an unusual event (UEV) handler routine.
摘要翻译： 一种固件控制单元的方法和装置，用于检测这种控制单元何时不能正常地运行。 控制单元被组织成包括在单元的控制存储器的每个位置，对于哪个控制不期望传送，包含指定该位置的地址的地址的预定类型的模式，标识不明原因的可能原因的合适标签 跳转，以及将控制权转移到控制商店内的报告固件例程中的适当入口点。 报告固件程序具有多个入口点，用于收集意外位置的所有执行，并将适当的地址和标签信息存储在预定的寄存器文件中，以便稍后通过异常事件（UEV）处理程序引用。
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公开(公告)号：US4799181A
公开(公告)日：1989-01-17
申请号：US913810
申请日：1986-09-30
申请人： Steven A. Tague , William E. Woods
发明人： Steven A. Tague , William E. Woods
摘要： A binary arithmetic unit performs arithmetic operations on binary coded decimal (BCD) operands by converting the BCD digits to hexadecimal excess 3 digits, generating hexadecimal excess 6 partial product digits and modifying selected excess 6 partial product digits to generate a BCD result.
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公开(公告)号：US4727486A
公开(公告)日：1988-02-23
申请号：US858786
申请日：1986-05-02
申请人： Michael D. Smith , Llewelyn S. Dunwell , Richard A. Lemay , Robert C. Miller , Theodore R. Staplin, Jr. , William E. Woods , John L. Curley
发明人： Michael D. Smith , Llewelyn S. Dunwell , Richard A. Lemay , Robert C. Miller , Theodore R. Staplin, Jr. , William E. Woods , John L. Curley
CPC分类号： G06F12/1054
摘要： A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.
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公开(公告)号：US4472773A
公开(公告)日：1984-09-18
申请号：US302897
申请日：1981-09-16
CPC分类号： G06F9/30
摘要： A decoding logic system in a logic control system of a data processing system is disclosed, wherein the data processing system is comprized of a main memory unit communicating with the logic control system by way of a common communication bus, and wherein the logic control system and a CPU (central processing unit) communicate by way of a local communication bus. In response to a CPU request, CPU instructions stored in the main memory unit are received by the logic decoding system, and presented to the CPU in such a manner as to accommodate both memory bit and CPU computed bit modifications to the instructions during instruction execution, while avoiding interruptions in CPU activity caused by information transfer delays internal to the logic decoding system. Instruction modification also may be effected by incrementing or decrementing the instructions under firmware control.
摘要翻译： 公开了一种数据处理系统的逻辑控制系统中的解码逻辑系统，其中数据处理系统由与公共通信总线与逻辑控制系统通信的主存储单元组成，其中逻辑控制系统和 CPU（中央处理单元）通过本地通信总线进行通信。 响应于CPU请求，存储在主存储器单元中的CPU指令由逻辑解码系统接收，并且以在指令执行期间容纳存储器位和CPU计算的位修改的方式呈现给CPU， 同时避免在逻辑解码系统内部的信息传输延迟引起的CPU活动中断。 也可以通过在固件控制下增加或减少指令来实现指令修改。
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9.发明授权Automatic operand length control of the result of a scientific arithmetic operation 失效自动操作数长度控制的科学算术运算结果
公开(公告)号：US4305134A
公开(公告)日：1981-12-08
申请号：US92619
申请日：1979-11-08
CPC分类号： G06F7/483 , G06F7/49947
摘要： Mantissa results of floating point operations are truncated to words of 24 bits each by storing the 64 bit mantissa result in a first address location of a random access memory, and storing binary ZEROs in the 48 least significant bit positions of a second address location of the random access memory. The mantissa result is truncated by addressing the high order 24 bits at the first address location and the 48 binary ZEROs at the second address location.
摘要翻译： 通过将64位尾数结果存储在随机存取存储器的第一地址位置中，将浮点运算的尾数结果截断为24位的字，并将二进制ZERO存储在第二地址位置的48个最低有效位位置 随机存取存储器。 通过寻址第一个地址位置的高位24位和第二个地址位置的48个二进制ZERO来截断尾数结果。
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10.发明授权Two stage selection based on time of arrival and predetermined priority in a bus priority resolver 失效基于总线优先级解算器的到达时间和预定优先级的两级选择
公开(公告)号：US4604685A
公开(公告)日：1986-08-05
申请号：US659012
申请日：1984-10-09
CPC分类号： G06F13/18
摘要： A priority resolver for providing unambiguous resolution of requests among competing processes vying for access to a common device and which is adapted to a non-distributed environment.
摘要翻译： 一种优先级解析器，用于在争夺访问公共设备的竞争过程中提供明确的请求解决方案，并适用于非分布式环境。
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