公开(公告)号：US5434628A

公开(公告)日：1995-07-18

申请号：US268078

申请日：1994-06-28

申请人： Richard C. Spiero ,  Terence A. Douglas ,  Marnix C. Vlot

发明人： Richard C. Spiero ,  Terence A. Douglas ,  Marnix C. Vlot

IPC分类号： H01R13/70 ,  H01R29/00 ,  H04N5/44 ,  H04N5/765 ,  H04N9/64 ,  H04N5/268

CPC分类号： H04N9/641 ,  H04N5/765 ,  Y10T307/735 ,  Y10T307/76 ,  Y10T307/858

摘要： The apparatus includes first, second and third connectors, a control signal generator (5.11) and first and second switches (5.9, 5.10). The first and second connectors each have a signal input terminal, a signal output terminal and a control signal terminal. The third connector has a signal input terminal (5.7) and eventually a control signal terminal (5.8). The first and second switching means each have first (a), second (b) and third (c) terminals, the first terminal (a) of the first switches (5.9) being coupled to the signal output terminal (5.5) of the second connector, the second terminal (b) of the first switches (5.9) being coupled to the signal input terminal (5.1) of the first connector, the first terminal (a) of the second switching means (5.10) being coupled to the signal output terminal (5.2) of the first connector, the second terminal (b) of the second switching means (5.10) being coupled to the signal input terminal (5.4) of the second connector. The first and second switches (5.9, 5.10) are adapted to couple the second (b) or the third (c) terminal to the first terminal (a) under the influence of a first or second control signal respectively, supplied by the control signal generator (5.11). The control signal generator (5.11) has a first terminal (10) coupled to the control signal terminals (5.3, 5.6) of the first and second connectors, and an output terminal (12, 13) for supplying the first and second control signal for the first and second switches (5.9, 5.10) respectively. The signal input terminal (5.7) of the third connector is coupled to the third terminals (c) of the first and second switches (5.9, 5.10). The control signal generator (5.11) is further adapted to generate a control signal for at least one of the first and the second switches, in response to the control signal applied to a second terminal (11).Further an input-output circuit is provided for coupling a controller included in the control signal generator (5.11) to line 10 of the SCART cable.

公开(公告)号：US5349391A

公开(公告)日：1994-09-20

申请号：US26348

申请日：1993-03-04

申请人： Richard C. Spiero ,  Terence A. Douglas ,  Marnix C. Vlot

发明人： Richard C. Spiero ,  Terence A. Douglas ,  Marnix C. Vlot

IPC分类号： H01R13/70 ,  H01R29/00 ,  H04N5/44 ,  H04N5/765 ,  H04N9/64 ,  H04N5/268

CPC分类号： H04N9/641 ,  H04N5/765 ,  Y10T307/735 ,  Y10T307/76 ,  Y10T307/858

摘要： The apparatus includes first, second and third connectors, a control signal generator (5.11) and first and second switches (5.9, 5.10). The first and second connector each have a signal input terminal, a signal output terminal and a control signal terminal. The third connector has a signal input terminal (5.7) and eventually a control signal terminal (5.8). The first and second switches each have first (a), second (b) and third (c) terminals, the first terminal (a) of the first switches (5.9) being coupled to the signal output terminal (5.5) of the second connector, the second terminal (b) of the first switches (5.9) being coupled to the signal input terminal (5.1) of the first connector, the first terminal (a) of the second switches (5.10) being coupled to the signal output terminal (5.2) of the first connector, the second terminal (b) of the second switches (5.10) being coupled to the signal input terminal (5.4) of the second connector. The first and second switches (5.9, 5.10) are adapted to couple the second (b) or the third (c) terminal to the first terminal (a) under the influence of a first or second control signal respectively, supplied by the control signal generator (5.11). The control signal generator (5.11) has a first terminal (10) coupled to the control signal terminals (5.3, 5.6) of the first and second connectors, and an output terminal (12, 13) for supplying the first and second control signal for the first and second switches (5.9, 5.10) respectively. The signal input terminal (5.7) of the third connector is coupled to the third terminals (c) of the first and second switches (5.9, 5.10). The control signal generator (5.11) is further adapted to generate a control signal for at least one of the first and the second switches, in response to the control signal applied to a second terminal (11). Further an input-output circuit is provided for coupling a controller included in the control signal generator (5.11) to line 10 of the SCART cable.

公开(公告)号：US5689507A

公开(公告)日：1997-11-18

申请号：US498291

申请日：1995-06-30

申请人： Rudolf H.J. Bloks ,  Marnix C. Vlot

发明人： Rudolf H.J. Bloks ,  Marnix C. Vlot

IPC分类号： H04J3/24 ,  H04L7/00 ,  H04L12/40 ,  H04L12/407 ,  H04L12/417 ,  H04L12/64 ,  H04N7/24 ,  H04N7/26 ,  H04N7/50 ,  H04N7/52 ,  H04L12/56

CPC分类号： H04L12/40058 ,  H04J3/247 ,  H04L12/40117 ,  H04L12/407 ,  H04L12/417 ,  H04L12/6418 ,  H04N19/42 ,  H04N19/61 ,  H04N21/4135 ,  H04N21/4305 ,  H04N21/4307 ,  H04N21/4342 ,  H04N21/43632 ,  H04L12/64 ,  H04L2012/6435 ,  H04L2012/6456 ,  H04L2012/6483 ,  H04L2012/6489

摘要： A signal processing system comprising a source apparatus coupled to a destination apparatus, the source apparatus being arranged for supplying the destination apparatus with a signal comprising video data, a time-stamp and synchronization data representing a time-value of an instant of said supplying, the destination apparatus being arranged for receiving the signal, synchronizing a time-value of a clock in accordance with the synchronization data, detecting when the time-value of the clock corresponds to the time-stamp and for thereupon presenting the video data at an output. The system includes a bus operable according to a time-slot allocation protocol, the source apparatus supplying the signal to the destination apparatus via the bus, the source apparatus including a first interface unit for buffering the signal until an allocated time-slot is available on the bus, the source apparatus setting the synchronization data according to an instant the signal is supplied to the first interface unit. The destination apparatus including a buffer, for buffering the signal prior to synchronizing the time-value of the clock for a predetermined interval, at least equal to a maximum wait-interval for the allocation of a time-slot on the bus, has elapsed after the instant the signal is supplied to the first interface unit.

摘要翻译： 一种信号处理系统，包括耦合到目的地设备的源设备，所述源设备被布置为向目的地设备提供包括视频数据的信号，时间戳和表示所述供应时刻的时间值的同步数据， 目的地装置被布置成用于接收信号，根据同步数据同步时钟的时间值，检测时钟的时间值对应于时间戳的时间，并且因此在输出端呈现视频数据 。 该系统包括可根据时隙分配协议操作的总线，源设备经由总线向目的地设备提供信号，源设备包括用于缓冲信号的第一接口单元，直到分配的时隙可用于 总线，源装置根据该信号被提供给第一接口单元的时刻设置同步数据。 包括缓冲器的目的地装置在用于在将时钟的时间值同步预定间隔之前缓冲信号至少等于用于分配总线上的时隙的最大等待间隔的缓冲器已经在 信号被提供给第一接口单元的瞬间。

公开(公告)号：US07124282B2

公开(公告)日：2006-10-17

申请号：US10000667

申请日：2001-11-15

申请人： Frederik Zandveld ,  Marnix C. Vlot

发明人： Frederik Zandveld ,  Marnix C. Vlot

IPC分类号： G06F12/00

CPC分类号： G06F9/3804 ,  G06F12/0607

摘要： Instructions for a processing unit are stored in a number of memory banks, successive instructions being stored in successive, different memory banks. Whenever execution of an instruction is started, the reading of one instruction which will be executed more than one instruction cycle later is also started. Consequently, a plurality of instructions are read in parallel from different memory banks. After the reading of an instruction, and before starting the execution of the instruction, the instruction passes through a pipeline in which the processing device detects whether the relevant instruction is a branch instruction. If this is so, the processing unit starts the reading in parallel of a number of instructions as from a branch target instruction. If it appears at a later stage that the branch is taken, said number of instructions is loaded into the pipeline in parallel.

公开(公告)号：US06502183B2

公开(公告)日：2002-12-31

申请号：US09128150

申请日：1998-08-03

申请人： Marnix C. Vlot ,  Paul E. R. Lippens

发明人： Marnix C. Vlot ,  Paul E. R. Lippens

IPC分类号： G06F1100

CPC分类号： G06F7/785 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/38 ,  G06F9/5016

摘要： The data processing device maintains two stacks. The length of the basic unit of information is different for each stack. Pops and pushes cause a change in the stack pointer which differs dependent on which stack is used. Instructions refer to different locations on the stack as registers defined by an offset of a number of basic units relative to the top of stack. In an embodiment a reference to registers is normally interpreted as a reference to one of a set of registers (including the top of stack register) without push or pop, but a reference to one register is interpreted as a reference to, top of stack including a push or pop.

摘要翻译： 数据处理设备维护两个堆栈。 信息的基本单位的长度对于每个堆栈是不同的。 弹出和推送会导致堆栈指针发生变化，这取决于使用哪个堆栈。 指令将堆栈中的不同位置指向由相对于堆栈顶部的基本单元的偏移量定义的寄存器。 在一个实施例中，对寄存器的引用通常被解释为对一组寄存器（包括堆栈寄存器的顶部）中的一个的引用而不是推或者弹出，但是对一个寄存器的引用被解释为对堆栈顶部的引用，包括 推或弹

公开(公告)号：US06182209B2

公开(公告)日：2001-01-30

申请号：US09135490

申请日：1998-08-17

申请人： Marnix C. Vlot ,  Paul E. R. Lippens

发明人： Marnix C. Vlot ,  Paul E. R. Lippens

IPC分类号： G06F932

CPC分类号： G06F7/785 ,  G06F9/30058 ,  G06F9/30163 ,  G06F9/322 ,  G06F9/5016

摘要： In an instruction a relative jump distance is expressed as a number of instructions rather than as a number of addresses. Instructions have various lengths. After encountering the instruction the processing device loads the following instructions but suppresses execution of a set of instructions that consists of the number of instructions expressed in the relative jump instruction.

摘要翻译： 在指令中，相对跳跃距离被表示为指令的数量而不是地址的数量。 说明书有不同的长度。 在遇到指令之后，处理设备加载以下指令，但是抑制由在相对跳转指令中表达的指令数量组成的指令集的执行。

公开(公告)号：US5787090A

公开(公告)日：1998-07-28

申请号：US896121

申请日：1997-07-17

申请人： Paulus A. W. Van Niekerk ,  Marnix C. Vlot

发明人： Paulus A. W. Van Niekerk ,  Marnix C. Vlot

IPC分类号： G11B31/00 ,  H04B1/16 ,  H04H20/28 ,  H04H20/34 ,  H04H60/07 ,  H05K11/00 ,  H04L5/00

CPC分类号： H04H20/28 ,  H04H20/34 ,  H04H60/07 ,  H04H2201/13

摘要： An audio system has an attacher station for attaching to and decoding an audio representation channel, which also has a first auxiliary information sub-channel. A user station is fed by the attacher station through a unidirectional interface and receives the auxiliary information in an application context under control of a user interface for selective displaying. The attacher station extracts the auxiliary information from the channel. The system also has a framework data generator that is instantiatable by information from the information sub-channel, and a framework packetizer fed by the generator for supplementing the audio representation channel on said unidirectional interface in a second auxiliary information sub-channel by packetized and instantiated application information for the user station.

摘要翻译： 音频系统具有用于附加和解码音频表示通道的附属站，该音频表示信道也具有第一辅助信息子信道。 由用户站通过单向接口由管理员站馈送，并且在用户界面的控制下在应用环境中接收辅助信息以进行选择性显示。 Attacher站从通道中提取辅助信息。 该系统还具有可由来自信息子信道的信息实例化的框架数据生成器，以及由发生器馈送的框架分组器，用于通过分组和实例化在第二辅助信息子信道中的所述单向接口上补充音频表示信道 用户站的应用信息。

公开(公告)号：US5594733A

公开(公告)日：1997-01-14

申请号：US943368

申请日：1992-09-10

申请人： Joost-Pieter Katoen ,  Marnix C. Vlot

发明人： Joost-Pieter Katoen ,  Marnix C. Vlot

IPC分类号： H04B17/00 ,  H04L12/28 ,  H04L29/06 ,  H04L29/14 ,  H04L12/403

CPC分类号： H04L12/2821 ,  H04L12/403 ,  H04L29/06 ,  H04L12/2807 ,  H04L2012/2849 ,  H04L2012/285

摘要： A communication system has multiple and uniformly weighted station interconnected by a shared digital bus. A particular station comprises globally relevant information, and, with a predetermined maximum recurrence time, transmits a data packet representing such item to any other interested station. If unanimous counter signalization occurs, the item is in order, other wise updating thereof is undertaken. The unanimity is either by positive signalization, or by default.

摘要翻译： 通信系统具有通过共享数字总线互连的多个均匀加权站。 特定站包括全局相关信息，并且在预定的最大重发时间内，将表示此类项目的数据分组发送到任何其他感兴趣的站点。 如果发生一致的计数器信号，则该项目按顺序进行，进行其他更新。 无论是通过积极的信号还是默认的一致性。

公开(公告)号：US06557093B2

公开(公告)日：2003-04-29

申请号：US09801081

申请日：2001-03-07

申请人： Marnix C. Vlot ,  Paul E. R. Lippens

发明人： Marnix C. Vlot ,  Paul E. R. Lippens

IPC分类号： G06F700

CPC分类号： G06F7/785 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/38 ,  G06F9/5016

摘要： The data processing device maintains two stacks. The length of the basic unit of information is different for each stack. Pops and pushes cause a change in the stack pointer which differs dependent on which stack is used. Instructions refer to different locations on the stack as registers defined by an offset of a number of basic units relative to the top of stack. In an embodiment a reference to registers is normally interpreted as a reference to one of a set of registers (including the top of stack register) without push or pop, but a reference to one register is interpreted as a reference to top of stack including a push or pop.

摘要翻译： 数据处理设备维护两个堆栈。 信息的基本单位的长度对于每个堆栈是不同的。 弹出和推送会导致堆栈指针发生变化，这取决于使用哪个堆栈。 指令将堆栈中的不同位置指向由相对于堆栈顶部的基本单元的偏移量定义的寄存器。 在一个实施例中，对寄存器的引用通常被解释为对一组寄存器（包括堆栈寄存器的顶部）中的一个的引用而不是推或者弹出，但是对一个寄存器的引用被解释为对堆栈顶部的引用，包括 推或流行

公开(公告)号：US06360311B1

公开(公告)日：2002-03-19

申请号：US08963937

申请日：1997-11-04

申请人： Frederik Zandveld ,  Marnix C. Vlot

发明人： Frederik Zandveld ,  Marnix C. Vlot

IPC分类号： G06F1200

CPC分类号： G06F9/3804 ,  G06F12/0607

摘要： Instructions for a processing unit are stored in a number of memory banks, successive instructions being stored in successive, different memory banks. Whenever execution of an instruction is started, the reading of one instruction which will be executed more than one instruction cycle later is also started. Consequently, a plurality of instructions are being read in parallel from different memory banks. After the reading of an instruction, and before starting the execution of the instruction, the instruction passes through a pipeline in which the processing device detects whether the relevant instruction is a branch instruction. If this is so, the processing unit starts the reading in parallel of a number of instructions as from a branch target instruction. If it appears at a later stage that the branch is taken, said number of instructions is loaded into the pipeline in parallel.

摘要翻译： 处理单元的指令被存储在多个存储体中，连续的指令被存储在连续的不同的存储体中。 无论何时开始执行指令，也开始读取将在多个指令周期后执行的一个指令。 因此，正在从不同的存储体并行读取多个指令。 在读取指令之后，并且在开始执行指令之前，指令通过处理设备检测相关指令是否是分支指令的流水线。 如果是这样，则处理单元从分支目标指令开始并行地读取多条指令。 如果在稍后阶段出现分支，则所述指令数并行加载到管道中。