公开(公告)号：US5358890A

公开(公告)日：1994-10-25

申请号：US47933

申请日：1993-04-19

申请人： Richard D. Sivan ,  James R. Pfiester

发明人： Richard D. Sivan ,  James R. Pfiester

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/302

CPC分类号： H01L21/76216 ,  H01L21/32

摘要： A process for forming isolation regions (20) having a self-aligned channel-stop (22) formed by implanting dopant atoms (24) through the isolation regions (22). An isolation mask (15) is formed over an active region (16) in a semiconductor substrate (10). The isolation mask can be constructed from a variety of materials including silicon nitride, silicon oxynitride, boron nitride, polysilicon, and germanium oxide. Thick isolation regions (20) are formed on either side of the isolation mask (15) and an ion implant process is carried out to form doped regions (22) in the substrate (10) immediately below the isolation regions (20). The isolation mask (15) prevents dopant atoms (24) from entering the active region (16) of the substrate (10).

摘要翻译： 一种用于形成具有通过将掺杂剂原子（24）通过隔离区域（22）注入而形成的自对准通道 - 停止（22）的隔离区域（20）的工艺。 隔离掩模（15）形成在半导体衬底（10）中的有源区（16）上。 隔离掩模可以由各种材料构成，包括氮化硅，氮氧化硅，氮化硼，多晶硅和氧化锗。 在隔离掩模（15）的任一侧上形成厚隔离区（20），并且执行离子注入工艺以在隔离区（20）正下方的衬底（10）中形成掺杂区（22）。 隔离掩模（15）防止掺杂剂原子（24）进入衬底（10）的有源区（16）。

公开(公告)号：US5229310A

公开(公告)日：1993-07-20

申请号：US887956

申请日：1992-05-26

申请人： Richard D. Sivan

发明人： Richard D. Sivan

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/6675 ,  H01L27/12 ,  H01L29/78642 ,  Y10S148/15

摘要： A thin-film transistor in a semiconductor device is self-aligned and vertically oriented. In one form of the present invention, the semiconductor device (10) has a vertical wall trench (18) formed in a first dielectric layer (16) and having a predetermined depth. A first current electrode (26) is formed on a bottom surface of the trench while a second current electrode (28) overlies the first dielectric material, each current electrode preferably being formed of polysilicon. A channel region (30) connecting the first and second current electrodes lies along the vertical wall of the trench and has a length substantially equal to the predetermined depth. A control electrode (36) is located within the trench and is also preferably formed of polysilicon. The control electrode is electrically isolated from the first current electrode and the channel region by a second dielectric layer (32).

摘要翻译： 半导体器件中的薄膜晶体管是自对准且垂直取向的。 在本发明的一种形式中，半导体器件（10）具有形成在第一介电层（16）中并具有预定深度的垂直壁沟槽（18）。 第一电流电极（26）形成在沟槽的底表面上，而第二电流电极（28）覆盖在第一介电材料上，每个电流电极优选地由多晶硅形成。 连接第一和第二电流电极的沟道区域（30）沿着沟槽的垂直壁设置，并且具有基本上等于预定深度的长度。 控制电极（36）位于沟槽内，并且还优选地由多晶硅形成。 控制电极通过第二电介质层（32）与第一电流电极和沟道区域电隔离。

公开(公告)号：US5541132A

公开(公告)日：1996-07-30

申请号：US408653

申请日：1995-03-21

申请人： Robert B. Davies ,  Vida Ilderem ,  Mark D. Griswold ,  Diann Dow ,  James E. Prendergast ,  Iksung Lim ,  Juan Buxo ,  Richard D. Sivan ,  James D. Burnett ,  Frank K. Baker

发明人： Robert B. Davies ,  Vida Ilderem ,  Mark D. Griswold ,  Diann Dow ,  James E. Prendergast ,  Iksung Lim ,  Juan Buxo ,  Richard D. Sivan ,  James D. Burnett ,  Frank K. Baker

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423 ,  H01L21/265

CPC分类号： H01L29/66659 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/42368 ,  Y10S438/981

摘要： An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor material (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).

摘要翻译： 具有减小的栅极 - 漏极电容的绝缘栅场效应晶体管（10）和制造场效应晶体管（10）的方法。 掺杂剂阱（13）形成在半导体材料（11）中。 栅极氧化物层（26）形成在掺杂剂阱（13）上，其中栅极氧化物层（26）和具有栅极接触部分（43）和栅极延伸部分（44）的栅极结构（41）。 栅极接触部分（43）允许与栅极结构（41）的电接触，而栅极延伸部分（44）用作有源栅极部分。 与栅极接触部分（43）相邻的栅极氧化物（26）的一部分被加厚以降低场效应晶体管（10）的栅极到漏极电容，从而增加绝缘栅极场效应晶体管（10）的带宽。

公开(公告)号：US5262352A

公开(公告)日：1993-11-16

申请号：US937025

申请日：1992-08-31

申请人： Michael P. Woo ,  James D. Hayden ,  Richard D. Sivan ,  Howard C. Kirsch ,  Bich-Yen Nguyen

发明人： Michael P. Woo ,  James D. Hayden ,  Richard D. Sivan ,  Howard C. Kirsch ,  Bich-Yen Nguyen

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/76831 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002

摘要： An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of conductive layer (14), and forming a sidewall of the conductive layer (18). An selective isotropic etch procedure is used to laterally recess the sidewall of the conductive layer (18). A sidewall spacer (22) is formed adjacent the sidewall of the conductive layer (18). A conductive layer (24) is formed within opening (19) and adjacent the spacer (22) to form an interconnection between conductive layers (24 and 14). The interconnection is self-aligned, and conductive layer (18) is reliably isolated from the interconnect due to the lateral recessed sidewall of the conductive layer (18).

摘要翻译： 形成具有衬底（10）的互连结构。 形成在衬底（10）上方的导电层（14）。 形成覆盖导电层（14）的导电层（18）。 通过导电层（18）蚀刻开口（19），暴露导电层（14）的顶部部分，并形成导电层（18）的侧壁。 使用选择性各向同性蚀刻工艺来横向凹入导电层（18）的侧壁。 邻近导电层（18）的侧壁形成侧壁间隔物（22）。 导电层（24）形成在开口（19）内并与隔离物（22）相邻以形成导电层（24和14）之间的互连。 互连是自对准的，并且由于导电层（18）的侧向凹入的侧壁，导电层（18）可靠地与互连隔离。

公开(公告)号：US5408130A

公开(公告)日：1995-04-18

申请号：US286592

申请日：1994-08-05

申请人： Michael P. Woo ,  James D. Hayden ,  Richard D. Sivan ,  Howard C. Kirsch ,  Bich-Yen Nguyen

发明人： Michael P. Woo ,  James D. Hayden ,  Richard D. Sivan ,  Howard C. Kirsch ,  Bich-Yen Nguyen

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/48 ,  H01L29/46 ,  H01L29/62

CPC分类号： H01L21/76831 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002

摘要： An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of conductive layer (14), and forming a sidewall of the conductive layer (18). An selective isotropic etch procedure is used to laterally recess the sidewall of the conductive layer (18). A sidewall spacer (22) is formed adjacent the sidewall of the conductive layer (18). A conductive layer (24) is formed within opening (19) and adjacent the spacer (22) to form an interconnection between conductive layers (24 and 14). The interconnection is self-aligned, and conductive layer (18) is reliably isolated from the interconnect due to the lateral recessed sidewall of the conductive layer (18).

摘要翻译： 形成具有衬底（10）的互连结构。 形成在衬底（10）上方的导电层（14）。 形成覆盖导电层（14）的导电层（18）。 通过导电层（18）蚀刻开口（19），暴露导电层（14）的顶部部分，并形成导电层（18）的侧壁。 使用选择性各向同性蚀刻工艺来横向凹入导电层（18）的侧壁。 邻近导电层（18）的侧壁形成侧壁间隔物（22）。 导电层（24）形成在开口（19）内并与隔离物（22）相邻以形成导电层（24和14）之间的互连。 互连是自对准的，并且由于导电层（18）的侧向凹入的侧壁，导电层（18）可靠地与互连隔离。

公开(公告)号：US5324973A

公开(公告)日：1994-06-28

申请号：US55582

申请日：1993-05-03

申请人： Richard D. Sivan

发明人： Richard D. Sivan

IPC分类号： H01L27/11 ,  H01L29/10

CPC分类号： H01L27/1108 ,  Y10S257/903

摘要： A semiconductor memory cell (10) includes vertically disposed MOS pass transistors (32, 34) and MOS inverters (12, 14) contained in trench structures in a semiconductor substrate (11). An MOS inverter (12) has a toroidal shared-gate electrode (48) overlying the wall surface of a first trench (36). A pass transistor (32) has a gate electrode (84) in a third trench (40). A first buried drain region (62) resides in the substrate (11) adjacent to the first trench (36), and is located a first distance from the substrate surface. A second buried drain region (64) resides in the substrate (11) adjacent to the second trench (32), and is located a second distance from the substrate surface. The inverter (12) and the pass transistor (32) are electrically coupled by the first and second buried layers (62, 64). The channel length (90) of the driver transistor (16) in the inverter (12) and the pass transistor (32) is determined by the first and second distances, respectively. Accordingly, the cell ratio of the memory cell (10) (ratio of W/L values) is also determined by the differential depth of the first and second buried drain regions (62, 64).

摘要翻译： 半导体存储单元（10）包括在半导体衬底（11）中包含在沟槽结构中的垂直设置的MOS通过晶体管（32,34）和MOS反相器（12,14）。 MOS反相器（12）具有覆盖在第一沟槽（36）的壁表面上的环形共享栅电极（48）。 传输晶体管（32）在第三沟槽（40）中具有栅电极（84）。 第一掩埋漏极区域（62）位于邻近第一沟槽（36）的衬底（11）中，并且位于离衬底表面的第一距离处。 第二埋漏区（64）驻留在与第二沟槽（32）相邻的衬底（11）中，并且位于离衬底表面的第二距离处。 逆变器（12）和通过晶体管（32）通过第一和第二掩埋层（62,64）电耦合。 逆变器（12）中的驱动晶体管（16）和通过晶体管（32）的沟道长度（90）分别由第一和第二距离决定。 因此，存储单元（10）的单元比（W / L值的比））也由第一和第二埋漏区（62,64）的差分深度确定。

公开(公告)号：US5285093A

公开(公告)日：1994-02-08

申请号：US955781

申请日：1992-10-05

申请人： Craig S. Lage ,  Richard D. Sivan

发明人： Craig S. Lage ,  Richard D. Sivan

IPC分类号： H01L27/11 ,  H01L29/786 ,  H01L29/10 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L29/78642 ,  H01L27/1108 ,  Y10S257/903

摘要： In one embodiment, a semiconductor memory cell (10) having a trench (24) and access transistor (54) formed in a well region (20). The trench (24) substantially contains an inverter (60) which is electrically coupled to ground and power signals by buried layers (12, 18) in the substrate (11). The inverter (60) has a toroidal, shared-gate electrode (40) which electrically controls a driver transistor (32) in the wall (26) of the trench (24), and a thin-film load transistor (42) in the central portion of the trench (24). A portion of the toroidal, shared gate electrode extends to an adjacent well region (20') and contacts well region (20') at cell node (13'). A ground signal is provided to load transistor (42) at the bottom surface (28) of the trench (42). A supply signal is provided by a buried layer (18) which is integral with driver transistor (32).

摘要翻译： 在一个实施例中，具有形成在阱区（20）中的沟槽（24）和存取晶体管（54）的半导体存储单元（10）。 沟槽（24）基本上包含逆变器（60），其通过衬底（11）中的掩埋层（12,18）电耦合到接地和功率信号。 逆变器（60）具有环形共用栅电极（40），其对沟槽（24）的壁（26）中的驱动晶体管（32）进行电控制，以及薄膜负载晶体管（42） 沟槽（24）的中心部分。 环形共享栅电极的一部分延伸到相邻的阱区（20'），并在单元节点（13'）处接触阱区（20'）。 提供接地信号以在沟槽（42）的底表面（28）处负载晶体管（42）。 电源信号由与驱动晶体管（32）成一体的掩埋层（18）提供。

公开(公告)号：US5006911A

公开(公告)日：1991-04-09

申请号：US415833

申请日：1989-10-02

申请人： Richard D. Sivan

发明人： Richard D. Sivan

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L29/45

CPC分类号： H01L29/66575 ,  H01L21/28525 ,  H01L29/456 ,  H01L29/665

摘要： A transistor device has a gate centered in an active region in which the gate does not extend beyond the active region. The active region has stem portion for the gate and a branch portion extending from each side of the stem portion for the formation of contacts. Raised polysilicon contacts are formed in the branch portions simultaneously with the gate being formed by selective polysilicon deposition. A source and drain are formed on sides of the gates while simultaneously doping the raised polysilicon contacts and the gate. A conformal insulator is etched to form holes to the raised contacts and the gate. These holes, even if over source and drain, do not penetrate to the source or drain because of the raised nature of the polysilicon contacts. Thus, the holes are filled with conductive material to form contacts over source and/or drain which do not contact source/drain. Thus there is no short from gate to source/drain even though the contact to gate is made over the active region. The gate, then, does not need to extend beyond the active region to provide for a metal contact thereto.

摘要翻译： 晶体管器件具有以有源区为中心的栅极，栅极不延伸超出有源区。 有源区域具有用于栅极的茎部分和从茎部分的每一侧延伸以形成接触的分支部分。 在通过选择性多晶硅沉积形成栅极的同时，在分支部分中形成凸起的多晶硅接触。 源极和漏极形成在栅极的侧面上，同时掺杂升高的多晶硅触点和栅极。 蚀刻保形绝缘体以向凸起的触点和栅极形成孔。 由于多晶硅触点的凸起性质，这些孔即使在源极和漏极之间也不会渗入源极或漏极。 因此，孔被导电材料填充以在源极和/或漏极上形成不接触源极/漏极的触点。 因此，尽管与栅极的接触在有源区域上进行，但是从栅极到源极/漏极也没有短路。 然后，栅极不需要延伸超过有源区域以提供与其的金属接触。

公开(公告)号：US5244824A

公开(公告)日：1993-09-14

申请号：US577727

申请日：1990-09-05

申请人： Richard D. Sivan

发明人： Richard D. Sivan

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10876 ,  H01L27/10823

摘要： A trench capacitor and transistor structure is formed in a semiconductor device. In one form, a transistor is fabricated within a cylindrical trench capacitor. The capacitor is formed within two displaced parallel planes in a substrate material, and has two electrodes which are separated by a dielectric material. The electrodes and dielectric are formed on a wall and a floor of the cylindrical trench. A column of epitaxial material is grown from the floor of the trench. A source region is formed by doping the top portion of the epitaxial column, and a drain region is formed by doping the floor of the trench. A gate electrode is deposited into the trench, creating a channel region along the sides of the epitaxial column. Thus, a transistor is also formed within the two displaced parallel planes in the substrate material.

摘要翻译： 在半导体器件中形成沟槽电容器和晶体管结构。 在一种形式中，在圆柱形沟槽电容器内制造晶体管。 电容器形成在衬底材料中的两个位移的平行平面内，并且具有由电介质材料分离的两个电极。 电极和电介质形成在圆柱形沟槽的壁和底板上。 从沟槽的底部生长出一列外延材料。 通过掺杂外延柱的顶部形成源极区，并且通过掺杂沟槽的底部形成漏极区。 栅电极沉积到沟槽中，沿着外延柱的侧面产生沟道区。 因此，晶体管也形成在衬底材料中的两个位移的平行平面内。

公开(公告)号：US5198683A

公开(公告)日：1993-03-30

申请号：US695053

申请日：1991-05-03

申请人： Richard D. Sivan

发明人： Richard D. Sivan

IPC分类号： G11C11/41 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/1104 ,  H01L29/78642 ,  Y10S257/903

摘要： A memory cell layout achieves a reduced cell area. In one embodiment, a six transitor (6T) SRAM cell has two vertical thin-film transistors (18 and 20) as load transistors, two transfer transistors (10 and 12), two latch transistors (14 and 16), and two storage nodes. NODE 1 and NODE 2 of the cell each have a minimum feature defined by trenches (60). Four of five interconnects associated with each node are located within the respective trench. For example in NODE 1, a drain of latch transistor (14), a gate of latch transistor (16), a drain of load transistor (18), and a current electrode of transfer transistor (10) are electrically coupled within or beneath one trench (60). A remaining interconnection of NODE 1, a gate of load transistor 20, is located within the trench associated with NODE 2. Thus, ten interconnects of the memory cell are contained within areas defined by two minimum features.

摘要翻译： 存储单元布局实现了减小的单元面积。 在一个实施例中，六位（6T）SRAM单元具有作为负载晶体管的两个垂直薄膜晶体管（18和20），两个传输晶体管（10和12），两个锁存晶体管（14和16）以及两个存储节点 。 单元的节点1和节点2各自具有由沟槽（60）限定的最小特征。 与每个节点相关联的五个互连中的四个位于相应的沟槽内。 例如在节点1中，锁存晶体管（14）的漏极，锁存晶体管（16）的栅极，负载晶体管（18）的漏极和传输晶体管（10）的电流电极电耦合在一个或多个 沟槽（60）。 NODE1的剩余互连，负载晶体管20的栅极位于与NODE2相关联的沟槽内。因此，存储器单元的十个互连包含在由两个最小特征限定的区域内。