公开(公告)号：US6128722A

公开(公告)日：2000-10-03

申请号：US23891

申请日：1998-02-13

申请人： Richard Edmund Fry ,  Dung Quoc Nguyen ,  Albert Thomas Williams

发明人： Richard Edmund Fry ,  Dung Quoc Nguyen ,  Albert Thomas Williams

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861

摘要： An apparatus for integer exception register (XER) renaming and methods of using the same are implemented. In a central processing unit (CPU) having a pipelined architecture, integer instructions that use or update the XER may be executed out-of-order using the XER renaming mechanism. Any instruction that updates the XER has an associated instruction identifier (IID) stored in a register. Subsequent instructions that use data in the XER use the stored IID to determine when the XER data has been updated by the execution of the instruction corresponding to the stored IID. As each instruction that updates XER data is executed, the data is stored in an XER rename buffer. Instructions using XER data then obtain the updated, valid, XER data from the rename buffer. In this way, these instructions can obtain valid XER data prior to completion of the preceding instructions. The XER data is retrieved from the XER rename buffer by indexing into the buffer by using an index derived from the stored IID. Because the updated XER data is available in the rename buffer before the updating instruction completes, out-of-order execution of instructions using or updating XER data is thereby realized.

摘要翻译： 实现了整数异常寄存器（XER）重命名的装置及其使用方法。 在具有流水线架构的中央处理单元（CPU）中，使用或更新XER的整数指令可以使用XER重命名机制执行无序。 更新XER的任何指令都具有存储在寄存器中的关联指令标识符（IID）。 使用XER中的数据的后续指令使用存储的IID来确定通过执行与存储的IID相对应的指令来更新XER数据的时间。 随着执行更新XER数据的每个指令，数据都存储在XER重命名缓冲区中。 使用XER数据的指令然后从重命名缓冲区获取更新的，有效的XER数据。 以这种方式，这些指令可以在完成前面的指令之前获得有效的XER数据。 通过使用从存储的IID导出的索引将索引到缓冲区中，从XER重命名缓冲区检索XER数据。 因为在更新指令完成之前更新的XER数据在重命名缓冲器中可用，从而实现了使用或更新XER数据的指令的无序执行。

公开(公告)号：US07290261B2

公开(公告)日：2007-10-30

申请号：US10422651

申请日：2003-04-24

申请人： William Elton Burky ,  Bjorn Peter Christensen ,  Dung Quoc Nguyen ,  David A. Schroter ,  Albert Thomas Williams

发明人： William Elton Burky ,  Bjorn Peter Christensen ,  Dung Quoc Nguyen ,  David A. Schroter ,  Albert Thomas Williams

IPC分类号： G06F9/46

CPC分类号： G06F9/3851 ,  G06F9/30076 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/384

摘要： A circuit and method provide rename register reallocation for simultaneous multi-threaded (SMT) processors that redistributes rename (mapped) resources between one thread during single-threaded (ST) execution and multiple threads during multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. The internal control logic then signals the resources to reallocate the resources. Rename resources are reallocated by directing an action at the rename mapper. When switching from SMT to ST mode, the mapper is directed to drop entries for the dying thread, but on a switch from ST to SMT mode, “dummy” instruction group dispatch indications are sent to the mapper that indicate use of all architected registers for each thread.

摘要翻译： 电路和方法为同时多线程（SMT）处理器提供重命名寄存器重新分配，该处理器在单线程（ST）执行期间的一个线程和多线程执行期间的多个线程之间重新分配重命名（映射）资源。 处理器接收指定从单线程转换到多线程模式或反之亦然的指令，并停止在处理器上执行的所有线程的执行。 内部控制逻辑然后发出资源重新分配资源。 重命名资源通过在重命名映射器处指示一个动作来重新分配。 当从SMT切换到ST模式时，映射器被定向到垂死线程的条目，但是在从ST到SMT模式的切换中，将“伪”指令组分派指示发送到映射器，指示使用所有架构的寄存器 每个线程。

公开(公告)号：US20100161945A1

公开(公告)日：2010-06-24

申请号：US12341930

申请日：2008-12-22

申请人： William E. Burky ,  Kurt A. Feiste ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Albert Thomas Williams

发明人： William E. Burky ,  Kurt A. Feiste ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Albert Thomas Williams

IPC分类号： G06F9/312

CPC分类号： G06F9/3834 ,  G06F9/3838 ,  G06F9/3851

摘要： An information handling system includes a processor that may perform issue queue virtual load/store instruction operations. The issue queue maintains load and store instructions with a real/virtual dependency flag. The issue queue provides storage resources for real and virtual load/store instructions. Real load/store instructions execute in a load store unit LSU. Virtual load/store instructions are pending execution in the LSU. The LSU may keep track of each virtual load/store instruction within the issue queue by thread, type, and pointer data. Provided that all dependencies are clear for a pending virtual load/store instruction, the LSU marks the pending virtual load/store instruction as real. The pending virtual load/store instruction may then issue to the LSU as a real load/store instruction.

摘要翻译： 信息处理系统包括可执行发布队列虚拟加载/存储指令操作的处理器。 问题队列通过实际/虚拟依赖标志来维护加载和存储指令。 问题队列为实际和虚拟加载/存储指令提供存储资源。 实际加载/存储指令在加载存储单元LSU中执行。 虚拟加载/存储指令正在等待在LSU中执行。 LSU可以通过线程，类型和指针数据跟踪发布队列内的每个虚拟加载/存储指令。 假设所有依赖关系对待处理的虚拟加载/存储指令都是清楚的，则LSU将待处理的虚拟加载/存储指令标记为真实的。 然后，挂起的虚拟加载/存储指令可以作为实际加载/存储指令发布到LSU。

公开(公告)号：US08041928B2

公开(公告)日：2011-10-18

申请号：US12341930

申请日：2008-12-22

申请人： William E. Burky ,  Kurt A. Feiste ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Albert Thomas Williams

发明人： William E. Burky ,  Kurt A. Feiste ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Albert Thomas Williams

IPC分类号： G06F9/00

CPC分类号： G06F9/3834 ,  G06F9/3838 ,  G06F9/3851

摘要： An information handling system includes a processor that may perform issue queue virtual load/store instruction operations. The issue queue maintains load and store instructions with a real/virtual dependency flag. The issue queue provides storage resources for real and virtual load/store instructions. Real load/store instructions execute in a load store unit LSU. Virtual load/store instructions are pending execution in the LSU. The LSU may keep track of each virtual load/store instruction within the issue queue by thread, type, and pointer data. Provided that all dependencies are clear for a pending virtual load/store instruction, the LSU marks the pending virtual load/store instruction as real. The pending virtual load/store instruction may then issue to the LSU as a real load/store instruction.

摘要翻译： 信息处理系统包括可执行发布队列虚拟加载/存储指令操作的处理器。 问题队列通过实际/虚拟依赖标志来维护加载和存储指令。 问题队列为实际和虚拟加载/存储指令提供存储资源。 实际加载/存储指令在加载存储单元LSU中执行。 虚拟加载/存储指令正在等待在LSU中执行。 LSU可以通过线程，类型和指针数据跟踪发布队列内的每个虚拟加载/存储指令。 假设所有依赖关系对待处理的虚拟加载/存储指令都是清楚的，则LSU将待处理的虚拟加载/存储指令标记为真实的。 然后，挂起的虚拟加载/存储指令可以作为实际加载/存储指令发布到LSU。

公开(公告)号：US08418180B2

公开(公告)日：2013-04-09

申请号：US12129876

申请日：2008-05-30

申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/46

CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

摘要： A method, apparatus, and computer program product are disclosed for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles by selecting the first thread to be a primary thread and the second thread to be a secondary thread. If a condition exists that requires overriding, an override state is executed by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.

摘要翻译： 公开了一种用于确保同时多线程（SMT）微处理器中的处理公平性的方法，装置和计算机程序产品。 在通过选择作为主线程的第一线程和第二线程成为辅线程的持续期望的时钟周期数的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 如果存在需要覆盖的条件，则通过选择作为主线程的第二个线程和第一个线程作为辅助线程来执行覆盖状态。 超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。 响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

公开(公告)号：US07663963B2

公开(公告)日：2010-02-16

申请号：US12134537

申请日：2008-06-06

申请人： Sam Gat-Shang Chu ,  Maureen Anne Delaney ,  Saiful Islam ,  Dung Quoc Nguyen ,  Jafar Nahidi

发明人： Sam Gat-Shang Chu ,  Maureen Anne Delaney ,  Saiful Islam ,  Dung Quoc Nguyen ,  Jafar Nahidi

IPC分类号： G11C8/00

CPC分类号： G06F9/30141

摘要： An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.

摘要翻译： 提供一种用于读取多个连续条目并使用2Read / 2Write寄存器文件仅写入一个读取地址和一个写入地址的多个连续条目的装置和方法。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 该装置和方法提供了通过仅对一个地址进行4到16个解码来写入连续条目的机制。 此外，该装置和方法提供了一种用于使用起始读字地址和基于起始读字地址生成的两个读字线从寄存器堆数组读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。

公开(公告)号：US20090063898A1

公开(公告)日：2009-03-05

申请号：US12270300

申请日：2008-11-13

申请人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

发明人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

IPC分类号： G06F11/20

CPC分类号： G06F12/0888 ,  G06F9/30043 ,  G06F9/3851 ,  G06F9/3863 ,  G06F11/1407

摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

摘要翻译： 恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。 恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。 处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。 允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。 如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

公开(公告)号：US07490226B2

公开(公告)日：2009-02-10

申请号：US11054289

申请日：2005-02-09

申请人： Hung Qui Le ,  Dung Quoc Nguyen ,  Raymond Cheung Yeung

发明人： Hung Qui Le ,  Dung Quoc Nguyen ,  Raymond Cheung Yeung

IPC分类号： G06F9/312

CPC分类号： G06F9/383 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3867

摘要： A method and related apparatus is provided for a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages, from an initial stage to a final write back stage. As a method, an embodiment includes the step of issuing a first instruction, such as an FMA instruction, to move through the sequence of execution stages, the first instruction being directed to a specified one of the registers. The method further includes issuing a second instruction to move through the execution stages, the second instruction being issued after the first instruction has issued, but before the first instruction reaches the final write back stage. The second instruction is likewise directed to the specified register, and comprises either a store instruction or a load instruction, selectively. R and W bits corresponding to the specified register are used to ensure that a store instruction does not read data from, and that a load instruction does not write data to the specified register, respectively, before the first instruction is moved to the final write back stage.

摘要翻译： 提供了一种用于具有多个寄存器的处理器的方法和相关装置，其中顺序地发出指令以从初始阶段到最终回写阶段移动经过一系列执行阶段。 作为一种方法，实施例包括发出诸如FMA指令的第一指令以移动经过执行级序列的步骤，第一指令被引导到指定的一个寄存器。 该方法还包括发出第二指令以移动通过执行阶段，第二指令在第一指令发出之后但在第一指令到达最终回写阶段之前发出。 第二条指令同样针对指定的寄存器，并且选择性地包括存储指令或加载指令。 使用与指定寄存器相对应的R和W位来确保存储指令不会从第一指令移动到最终回写之前分别读取数据，并且加载指令不会将数据写入指定的寄存器 阶段。

公开(公告)号：US07467325B2

公开(公告)日：2008-12-16

申请号：US11055258

申请日：2005-02-10

申请人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

发明人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

IPC分类号： G06F11/00

CPC分类号： G06F12/0888 ,  G06F9/30043 ,  G06F9/3851 ,  G06F9/3863 ,  G06F11/1407

摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

摘要翻译： 恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。 恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。 处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。 允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。 如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

公开(公告)号：US20080222395A1

公开(公告)日：2008-09-11

申请号：US11683843

申请日：2007-03-08

申请人： Hung Qui Le ,  Dung Quoc Nguyen

发明人： Hung Qui Le ,  Dung Quoc Nguyen

IPC分类号： G06F9/44

CPC分类号： G06F9/3836 ,  G06F9/3824 ,  G06F9/3857 ,  G06F9/3859

摘要： A system and method for predictive early allocation of stores in a microprocessor is presented. During instruction dispatch, an instruction dispatch unit retrieves an instruction from an instruction cache (Icache). When the retrieved instruction is an interruptible instruction, the instruction dispatch unit loads the interruptible instruction's instruction tag (IITAG) into an interruptible instruction tag register. A load store unit loads subsequent instruction information (instruction tag and store data) along with the interruptible instruction tag in a store data queue entry. Comparison logic receives a completing instruction tag from completion logic, and compares the completing instruction tag with the interruptible instruction tags included in the store data queue entries. In turn, deallocation logic deallocates those store data queue entries that include an interruptible instruction tag that matches the completing instruction tag.

摘要翻译： 提出了一种用于在微处理器中预先提前存储分配的系统和方法。 在指令调度期间，指令调度单元从指令高速缓存（Icache）检索指令。 当检索到的指令是可中断指令时，指令调度单元将可中断指令的指令标记（IITAG）加载到可中断指令标记寄存器中。 加载存储单元将后续指令信息（指令标签和存储数据）与可中断指令标签一起存储在存储数据队列条目中。 比较逻辑从完成逻辑接收完成指令标记，并将完成指令标签与包含在存储数据队列条目中的可中断指令标签进行比较。 反过来，解配分配逻辑会释放那些包含与完成指令标记匹配的可中断指令标签的存储数据队列条目。