公开(公告)号：US07290261B2

公开(公告)日：2007-10-30

申请号：US10422651

申请日：2003-04-24

申请人： William Elton Burky ,  Bjorn Peter Christensen ,  Dung Quoc Nguyen ,  David A. Schroter ,  Albert Thomas Williams

发明人： William Elton Burky ,  Bjorn Peter Christensen ,  Dung Quoc Nguyen ,  David A. Schroter ,  Albert Thomas Williams

IPC分类号： G06F9/46

CPC分类号： G06F9/3851 ,  G06F9/30076 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/384

摘要： A circuit and method provide rename register reallocation for simultaneous multi-threaded (SMT) processors that redistributes rename (mapped) resources between one thread during single-threaded (ST) execution and multiple threads during multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. The internal control logic then signals the resources to reallocate the resources. Rename resources are reallocated by directing an action at the rename mapper. When switching from SMT to ST mode, the mapper is directed to drop entries for the dying thread, but on a switch from ST to SMT mode, “dummy” instruction group dispatch indications are sent to the mapper that indicate use of all architected registers for each thread.

摘要翻译： 电路和方法为同时多线程（SMT）处理器提供重命名寄存器重新分配，该处理器在单线程（ST）执行期间的一个线程和多线程执行期间的多个线程之间重新分配重命名（映射）资源。 处理器接收指定从单线程转换到多线程模式或反之亦然的指令，并停止在处理器上执行的所有线程的执行。 内部控制逻辑然后发出资源重新分配资源。 重命名资源通过在重命名映射器处指示一个动作来重新分配。 当从SMT切换到ST模式时，映射器被定向到垂死线程的条目，但是在从ST到SMT模式的切换中，将“伪”指令组分派指示发送到映射器，指示使用所有架构的寄存器 每个线程。

公开(公告)号：US20100250900A1

公开(公告)日：2010-09-30

申请号：US12409934

申请日：2009-03-24

申请人： Mary Douglass Brown ,  William Elton Burky ,  Dung Quoc Nguyen ,  Balaram Sinharoy

发明人： Mary Douglass Brown ,  William Elton Burky ,  Dung Quoc Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3814 ,  G06F9/3838

摘要： An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions along with relative instruction to instruction dependency information. A mapper maps queue position data for instructions that dispatch to issue queue locations within the IU. The IU may test an issuing producer instruction against consumer instructions in the IU for queue position (QPOS) and register tag (RTAG) matches. A matching consumer instruction may issue in a successive manner in the case of a queue position match or in a next processor cycle in the case of a register tag match.

摘要翻译： 信息处理系统包括具有发布单元（IU）的处理器，该单元可对连续指令发布操作执行指令依赖性跟踪。 IU保持非移位问题队列（NSIQ）和移位发送队列（SIQ）指令以及与指令依赖信息的相关指令。 映射器映射队列位置数据，用于发送在IU内发出队列位置的指令。 IU可以根据IU中的消费者指令测试发出生产者指令的队列位置（QPOS）和注册标签（RTAG）匹配。 在队列位置匹配的情况下，或者在注册标签匹配的情况下，在下一个处理器周期中，匹配的消费者指令可以以连续的方式发布。

公开(公告)号：US06275918B1

公开(公告)日：2001-08-14

申请号：US09268307

申请日：1999-03-16

申请人： William Elton Burky ,  Peter Steven Lenk ,  Dung Quoc Nguyen ,  David Andrew Schroter ,  Shih-Hsiung Stephen Tung ,  Michael Thomas Vaden

发明人： William Elton Burky ,  Peter Steven Lenk ,  Dung Quoc Nguyen ,  David Andrew Schroter ,  Shih-Hsiung Stephen Tung ,  Michael Thomas Vaden

IPC分类号： G06F934

CPC分类号： G06F9/383 ,  G06F9/3455 ,  G06F9/3832

摘要： A method and system for improving pre-fetch accuracy in a data processing system utilizing a pre-fetch history table is disclosed. The method compares a portion of an instruction address to an address located as an entry in a pre-fetch history table based on the status of a validity bit contained in the entry. If the validity bit is set and the addresses match, an indicator field within the entry is checked to see if it is equal to or greater than a threshold level. When the indicator field is greater than the threshold level, a target operand address is pre-fetched based on stride and direction.

摘要翻译： 公开了一种利用预取历史表改善数据处理系统中的预取精度的方法和系统。 该方法基于条目中包含的有效位的状态，将指令地址的一部分与位于预取历史表中的条目的地址进行比较。 如果有效位被设置并且地址匹配，则检查条目内的指示符字段以查看其是否等于或大于阈值级别。 当指示符字段大于阈值电平时，将根据步幅和方向预取目标操作数地址。

公开(公告)号：US08108655B2

公开(公告)日：2012-01-31

申请号：US12410073

申请日：2009-03-24

申请人： Christopher Michael Abernathy ,  James Wilson Bishop ,  Mary Douglass Brown ,  William Elton Burky ,  Robert Allen Cordes ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Todd Alan Venton

发明人： Christopher Michael Abernathy ,  James Wilson Bishop ,  Mary Douglass Brown ,  William Elton Burky ,  Robert Allen Cordes ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Todd Alan Venton

IPC分类号： G06F9/302 ,  G06F9/312

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3885

摘要： Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by both a fixed point execution unit and a load-store execution unit. In turn, the issue logic determines that the unified payload does not include a load-store instruction that is ready to issue. As a result, the issue logic issues the simple fixed point instruction to the load-store execution unit in response to determining that the simple fixed point instruction is ready to issue and determining that the unified payload does not include a load-store instruction that is ready to issue.

摘要翻译： 问题逻辑标识一个简单的固定点指令，包含在一个准备发布的统一有效载荷中。 简单的固定点指令是一种可由固定点执行单元和加载存储执行单元执行的指令。 反过来，问题逻辑确定统一有效载荷不包括准备发布的加载存储指令。 结果，响应于确定简单的固定点指令准备发出并且确定统一的有效载荷不包括加载存储指令，问题逻辑将简单的固定点指令发布到加载存储执行单元 准备发行。

公开(公告)号：US08086826B2

公开(公告)日：2011-12-27

申请号：US12409934

申请日：2009-03-24

申请人： Mary Douglass Brown ,  William Elton Burky ,  Dung Quoc Nguyen ,  Balaram Sinharoy

发明人： Mary Douglass Brown ,  William Elton Burky ,  Dung Quoc Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/38 ,  G06F9/52

CPC分类号： G06F9/3814 ,  G06F9/3838

摘要： An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions along with relative instruction to instruction dependency information. A mapper maps queue position data for instructions that dispatch to issue queue locations within the IU. The IU may test an issuing producer instruction against consumer instructions in the IU for queue position (QPOS) and register tag (RTAG) matches. A matching consumer instruction may issue in a successive manner in the case of a queue position match or in a next processor cycle in the case of a register tag match.

摘要翻译： 信息处理系统包括具有发布单元（IU）的处理器，该单元可对连续指令发布操作执行指令依赖性跟踪。 IU保持非移位问题队列（NSIQ）和移位发送队列（SIQ）指令以及与指令依赖信息的相关指令。 映射器映射队列位置数据，用于发送在IU内发出队列位置的指令。 IU可以根据IU中的消费者指令测试发出生产者指令的队列位置（QPOS）和注册标签（RTAG）匹配。 在队列位置匹配的情况下，或者在注册标签匹配的情况下，在下一个处理器周期中，匹配的消费者指令可以以连续的方式发布。

公开(公告)号：US20100250901A1

公开(公告)日：2010-09-30

申请号：US12410073

申请日：2009-03-24

申请人： Christopher Michael Abernathy ,  James Wilson Bishop ,  Mary Douglass Brown ,  William Elton Burky ,  Robert Allen Cordes ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Todd Alan Venton

发明人： Christopher Michael Abernathy ,  James Wilson Bishop ,  Mary Douglass Brown ,  William Elton Burky ,  Robert Allen Cordes ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Todd Alan Venton

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3885

摘要： Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by both a fixed point execution unit and a load-store execution unit. In turn, the issue logic determines that the unified payload does not include a load-store instruction that is ready to issue. As a result, the issue logic issues the simple fixed point instruction to the load-store execution unit in response to determining that the simple fixed point instruction is ready to issue and determining that the unified payload does not include a load-store instruction that is ready to issue.

摘要翻译： 问题逻辑标识一个简单的固定点指令，包含在一个准备发布的统一有效载荷中。 简单的固定点指令是一种可由固定点执行单元和加载存储执行单元执行的指令。 反过来，问题逻辑确定统一有效载荷不包括准备发布的加载存储指令。 结果，响应于确定简单的固定点指令准备发出并且确定统一的有效载荷不包括加载存储指令，问题逻辑将简单的固定点指令发布到加载存储执行单元 准备发行。

公开(公告)号：US6128722A

公开(公告)日：2000-10-03

申请号：US23891

申请日：1998-02-13

申请人： Richard Edmund Fry ,  Dung Quoc Nguyen ,  Albert Thomas Williams

发明人： Richard Edmund Fry ,  Dung Quoc Nguyen ,  Albert Thomas Williams

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861

摘要： An apparatus for integer exception register (XER) renaming and methods of using the same are implemented. In a central processing unit (CPU) having a pipelined architecture, integer instructions that use or update the XER may be executed out-of-order using the XER renaming mechanism. Any instruction that updates the XER has an associated instruction identifier (IID) stored in a register. Subsequent instructions that use data in the XER use the stored IID to determine when the XER data has been updated by the execution of the instruction corresponding to the stored IID. As each instruction that updates XER data is executed, the data is stored in an XER rename buffer. Instructions using XER data then obtain the updated, valid, XER data from the rename buffer. In this way, these instructions can obtain valid XER data prior to completion of the preceding instructions. The XER data is retrieved from the XER rename buffer by indexing into the buffer by using an index derived from the stored IID. Because the updated XER data is available in the rename buffer before the updating instruction completes, out-of-order execution of instructions using or updating XER data is thereby realized.

摘要翻译： 实现了整数异常寄存器（XER）重命名的装置及其使用方法。 在具有流水线架构的中央处理单元（CPU）中，使用或更新XER的整数指令可以使用XER重命名机制执行无序。 更新XER的任何指令都具有存储在寄存器中的关联指令标识符（IID）。 使用XER中的数据的后续指令使用存储的IID来确定通过执行与存储的IID相对应的指令来更新XER数据的时间。 随着执行更新XER数据的每个指令，数据都存储在XER重命名缓冲区中。 使用XER数据的指令然后从重命名缓冲区获取更新的，有效的XER数据。 以这种方式，这些指令可以在完成前面的指令之前获得有效的XER数据。 通过使用从存储的IID导出的索引将索引到缓冲区中，从XER重命名缓冲区检索XER数据。 因为在更新指令完成之前更新的XER数据在重命名缓冲器中可用，从而实现了使用或更新XER数据的指令的无序执行。

公开(公告)号：US20100161945A1

公开(公告)日：2010-06-24

申请号：US12341930

申请日：2008-12-22

申请人： William E. Burky ,  Kurt A. Feiste ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Albert Thomas Williams

发明人： William E. Burky ,  Kurt A. Feiste ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Albert Thomas Williams

IPC分类号： G06F9/312

CPC分类号： G06F9/3834 ,  G06F9/3838 ,  G06F9/3851

摘要： An information handling system includes a processor that may perform issue queue virtual load/store instruction operations. The issue queue maintains load and store instructions with a real/virtual dependency flag. The issue queue provides storage resources for real and virtual load/store instructions. Real load/store instructions execute in a load store unit LSU. Virtual load/store instructions are pending execution in the LSU. The LSU may keep track of each virtual load/store instruction within the issue queue by thread, type, and pointer data. Provided that all dependencies are clear for a pending virtual load/store instruction, the LSU marks the pending virtual load/store instruction as real. The pending virtual load/store instruction may then issue to the LSU as a real load/store instruction.

摘要翻译： 信息处理系统包括可执行发布队列虚拟加载/存储指令操作的处理器。 问题队列通过实际/虚拟依赖标志来维护加载和存储指令。 问题队列为实际和虚拟加载/存储指令提供存储资源。 实际加载/存储指令在加载存储单元LSU中执行。 虚拟加载/存储指令正在等待在LSU中执行。 LSU可以通过线程，类型和指针数据跟踪发布队列内的每个虚拟加载/存储指令。 假设所有依赖关系对待处理的虚拟加载/存储指令都是清楚的，则LSU将待处理的虚拟加载/存储指令标记为真实的。 然后，挂起的虚拟加载/存储指令可以作为实际加载/存储指令发布到LSU。

公开(公告)号：US08041928B2

公开(公告)日：2011-10-18

申请号：US12341930

申请日：2008-12-22

申请人： William E. Burky ,  Kurt A. Feiste ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Albert Thomas Williams

发明人： William E. Burky ,  Kurt A. Feiste ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Albert Thomas Williams

IPC分类号： G06F9/00

CPC分类号： G06F9/3834 ,  G06F9/3838 ,  G06F9/3851

摘要： An information handling system includes a processor that may perform issue queue virtual load/store instruction operations. The issue queue maintains load and store instructions with a real/virtual dependency flag. The issue queue provides storage resources for real and virtual load/store instructions. Real load/store instructions execute in a load store unit LSU. Virtual load/store instructions are pending execution in the LSU. The LSU may keep track of each virtual load/store instruction within the issue queue by thread, type, and pointer data. Provided that all dependencies are clear for a pending virtual load/store instruction, the LSU marks the pending virtual load/store instruction as real. The pending virtual load/store instruction may then issue to the LSU as a real load/store instruction.

摘要翻译： 信息处理系统包括可执行发布队列虚拟加载/存储指令操作的处理器。 问题队列通过实际/虚拟依赖标志来维护加载和存储指令。 问题队列为实际和虚拟加载/存储指令提供存储资源。 实际加载/存储指令在加载存储单元LSU中执行。 虚拟加载/存储指令正在等待在LSU中执行。 LSU可以通过线程，类型和指针数据跟踪发布队列内的每个虚拟加载/存储指令。 假设所有依赖关系对待处理的虚拟加载/存储指令都是清楚的，则LSU将待处理的虚拟加载/存储指令标记为真实的。 然后，挂起的虚拟加载/存储指令可以作为实际加载/存储指令发布到LSU。

公开(公告)号：US08418180B2

公开(公告)日：2013-04-09

申请号：US12129876

申请日：2008-05-30

申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/46

CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

摘要： A method, apparatus, and computer program product are disclosed for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles by selecting the first thread to be a primary thread and the second thread to be a secondary thread. If a condition exists that requires overriding, an override state is executed by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.

摘要翻译： 公开了一种用于确保同时多线程（SMT）微处理器中的处理公平性的方法，装置和计算机程序产品。 在通过选择作为主线程的第一线程和第二线程成为辅线程的持续期望的时钟周期数的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 如果存在需要覆盖的条件，则通过选择作为主线程的第二个线程和第一个线程作为辅助线程来执行覆盖状态。 超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。 响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。