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    Programmable logic array integrated circuit devices
    3.
    发明授权
    Programmable logic array integrated circuit devices 失效
    可编程逻辑阵列集成电路器件

    公开(公告)号：US5986470A

    公开(公告)日：1999-11-16

    申请号：US970830

    申请日：1997-11-14

    申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  Rina Raman ,  L. Todd Cope ,  Joseph Huang ,  Bruce B. Pedersen

    发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  Rina Raman ,  L. Todd Cope ,  Joseph Huang ,  Bruce B. Pedersen

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

    摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

    摘要翻译： 可编程逻辑阵列集成电路器件包括以有意义的行和列的二维阵列布置在器件上的多个可编程逻辑区域。 互连导体与每行和列相关联。 与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。 为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。 逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。 还提供了许多其他增强功能。

    Programmable logic array integrated circuit devices
    7.
    发明授权
    Programmable logic array integrated circuit devices 失效
    可编程逻辑阵列集成电路器件

    公开(公告)号：US5689195A

    公开(公告)日：1997-11-18

    申请号：US442795

    申请日：1995-05-17

    申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  Rina Raman ,  L. Todd Cope ,  Joseph Huang ,  Bruce B. Pedersen

    发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  Rina Raman ,  L. Todd Cope ,  Joseph Huang ,  Bruce B. Pedersen

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

    摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

    摘要翻译： 可编程逻辑阵列集成电路器件包括以有意义的行和列的二维阵列布置在器件上的多个可编程逻辑区域。 互连导体与每行和列相关联。 与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。 为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。 逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。 还提供了许多其他增强功能。

    Techniques for programming programmable logic array devices
    8.
    发明授权
    Techniques for programming programmable logic array devices 失效
    用于编程可编程逻辑阵列器件的技术

    公开(公告)号：US06191608B1

    公开(公告)日：2001-02-20

    申请号：US08851250

    申请日：1997-05-05

    申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  Kerry Veenstra ,  Andreas Papaliolios ,  Chiakang Sung ,  Richard Shaw Terrill ,  Rina Raman ,  Robert Richard Noel Bielby

    发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  Kerry Veenstra ,  Andreas Papaliolios ,  Chiakang Sung ,  Richard Shaw Terrill ,  Rina Raman ,  Robert Richard Noel Bielby

    IPC分类号： H03K19177

    CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/1774 ,  H03K19/17748

    摘要： Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

    摘要翻译： 可编程逻辑阵列器件由网络中的编程设备编程，这些器件可以利用任何大小或复杂度的程序来编程任何数量的这种逻辑器件。 编程数据和控制的源可以是微处理器或一个或多个串行EPROM，一个EPROM配备有时钟电路。 可以使用几个并行数据流来加速编程操作。 可以提供具有可编程可变速度的时钟电路以便于具有不同速度特性的编程逻辑器件。 编程协议可以包括在每个编程数据传输之后从逻辑设备到编程数据源的确认，使得源可以以逻辑设备能够接受该数据的速度自动发送编程数据。

    Programmable logic devices with spare circuits for replacement of defects
    10.
    发明授权
    Programmable logic devices with spare circuits for replacement of defects 失效
    具有备用电路的可编程逻辑器件可用于更换缺陷

    公开(公告)号：US5434514A

    公开(公告)日：1995-07-18

    申请号：US979003

    申请日：1992-11-19

    申请人： Richard G. Cliff ,  Rina Raman ,  Srinivas T. Reddy

    发明人： Richard G. Cliff ,  Rina Raman ,  Srinivas T. Reddy

    IPC分类号： H01L21/82 ,  G06F11/20 ,  H03K19/003 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1737 ,  H03K19/00392

    摘要： A programmable, integrated circuit, logic array device has several regular logic groups and at least one spare logic group. If any of the regular logic groups is defective, the spare logic group is used to make up for the defective logic group. To accomplish this, programming and data input signals that would normally go to the defective logic group are redirected to another logic group. The data output signals of the other group are substituted for the data output signals of the logic group that would normally have received the programming and data input signals that were redirected to the other logic group.

    摘要翻译： 可编程的集成电路逻辑阵列器件具有多个常规逻辑组和至少一个备用逻辑组。 如果任何常规逻辑组有故障，则备用逻辑组用于弥补故障逻辑组。 为了实现这一点，通常去故障逻辑组的编程和数据输入信号被重定向到另一个逻辑组。 另一组的数据输出信号代替通常已经接收到编程的逻辑组的数据输出信号和被重定向到另一个逻辑组的数据输入信号。