公开(公告)号：US20090276075A1

公开(公告)日：2009-11-05

申请号：US12366211

申请日：2009-02-05

申请人： Richard Good ,  Matthew Purdy

发明人： Richard Good ,  Matthew Purdy

IPC分类号： G06F19/00 ,  G06N5/02 ,  G06F17/10

CPC分类号： G07C3/146 ,  G06Q10/06

摘要： In a complex manufacturing environment for producing semiconductor devices, a predicted quality distribution in the form of a graded die forecast may be monitored with respect to changes in order to more efficiently identify factory disturbances. To this end, a predicted distribution obtained on the basis of electrical measurement data may be compared with a predicted yield distribution based on other production data. That is, an efficient automatic monitoring of the manufacturing environment may be accomplished with reduced probability of missing respective disturbance situations, since the large number of electrical parameters may be condensed into the predicted quality distribution.

摘要翻译： 在用于生产半导体器件的复杂制造环境中，可以针对变化来监视梯度模具预测形式的预测质量分布，以更有效地识别工厂干扰。 为此，可以将基于电测量数据获得的预测分布与基于其他生产数据的预测产量分布进行比较。 也就是说，由于可以将大量的电参数集中到预测的质量分布中，所以可以以减少各个干扰情况的概率降低来实现制造环境的有效的自动监视。

公开(公告)号：US10314596B2

公开(公告)日：2019-06-11

申请号：US13291855

申请日：2011-11-08

申请人： Matthew Purdy ,  Lucile Ferrand ,  Pierric Deransart

发明人： Matthew Purdy ,  Lucile Ferrand ,  Pierric Deransart

IPC分类号： A61B17/16 ,  A61B17/17

摘要： Embodiments of the invention include an orthopedic milling machine for preparing a glenoid bone. The milling machine uses a hub and a sleeve. The hub includes reliefs arranged to cut or mill the bone and the sleeve couples to the hub to transfer rotational motion to the hub. The hub has an axial bore sized to receive an orthopedic guide pin. The hub also has a lateral passage slot that allows the hub to move laterally towards the guide pin in order to place the guide pin within the axial bore.

公开(公告)号：US20060025879A1

公开(公告)日：2006-02-02

申请号：US10909606

申请日：2004-08-02

申请人： Matthew Purdy

发明人： Matthew Purdy

IPC分类号： G06F19/00

CPC分类号： G05B19/41865 ,  Y02P90/20

摘要： The present invention is generally directed to various methods and systems for prioritizing material to clear exception conditions. In one illustrative embodiment, the method includes providing a plurality of workpieces, each of the workpieces having an associated quantity of material that cannot be processed until the workpiece has been processed, and determining a priority for processing each of the plurality of workpieces based upon at least the associated quantity of material that cannot be processed.

摘要翻译： 本发明一般涉及用于优先处理材料以清除异常情况的各种方法和系统。 在一个说明性实施例中，该方法包括提供多个工件，每个工件具有在工件被处理之前不能被加工的相关数量的材料，并且基于在...处确定用于处理多个工件中的每一个的优先级 至少不能处理的材料的相关数量。

公开(公告)号：US6133132A

公开(公告)日：2000-10-17

申请号：US488605

申请日：2000-01-20

申请人： Anthony J. Toprac ,  John R. Behnke ,  Matthew Purdy

发明人： Anthony J. Toprac ,  John R. Behnke ,  Matthew Purdy

IPC分类号： H01L21/336 ,  H01L21/66 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/66575 ,  H01L22/20 ,  H01L29/6659

摘要： A method for controlling spacer width in a semiconductor device is provided. A substrate having a gate formed thereon is provided. An insulative layer is formed over at least a portion of the substrate. The insulative layer covers the gate. The thickness of the insulative layer is measured. A portion of the insulative layer to be removed is determined based on the measured thickness of the insulative layer. The portion of the insulative layer is removed to define a spacer on the gate. A processing line for forming a spacer on a gate disposed on a substrate includes a deposition tool, a thickness metrology tool, and automatic process controller, and a spacer etch tool. The deposition tool is adapted to form an insulative layer over at least a portion of the substrate. The insulative layer covers the gate. The thickness metrology tool is adapted to measure the thickness of the insulative layer. The automatic process controller is adapted to determine a portion of the insulative layer to be removed based on the measured thickness of the insulative layer. The spacer etch tool is adapted to remove the portion of the insulative layer to define a spacer on the gate.

摘要翻译： 提供了一种用于控制半导体器件中的间隔物宽度的方法。 提供其上形成有栅极的基板。 在衬底的至少一部分上形成绝缘层。 绝缘层覆盖门。 测量绝缘层的厚度。 基于所测量的绝缘层的厚度来确定要去除的绝缘层的一部分。 去除绝缘层的部分以在栅极上限定间隔物。 用于在设置在基板上的栅极上形成间隔物的处理线包括沉积工具，厚度计量工具和自动过程控制器以及间隔物蚀刻工具。 沉积工具适于在衬底的至少一部分上形成绝缘层。 绝缘层覆盖门。 厚度测量工具适用于测量绝缘层的厚度。 自动处理控制器适于基于所测量的绝缘层的厚度来确定要去除的绝缘层的一部分。 间隔蚀刻工具适于去除绝缘层的部分以在栅极上限定间隔物。

公开(公告)号：US20060095232A1

公开(公告)日：2006-05-04

申请号：US10979309

申请日：2004-11-02

申请人： Matthew Purdy

发明人： Matthew Purdy

IPC分类号： G21C17/00

CPC分类号： G05B23/0221

摘要： A method, apparatus and a system, for provided for performing a dynamic weighting technique for performing fault detection. The method comprises processing a workpiece and performing a fault detection analysis relating to the processing of the workpiece. The method further comprises determining a relationship of a parameter relating to the fault detection analysis to a detected fault and adjusting a weighting associated with the parameter based upon the relationship of the parameter to the detected fault.

摘要翻译： 一种用于执行用于执行故障检测的动态加权技术的方法，装置和系统。 该方法包括处理工件并执行与工件的处理有关的故障检测分析。 该方法还包括根据参数与检测到的故障的关系，确定与故障检测分析有关的参数与检测到的故障的关系，并调整与参数相关联的加权。

公开(公告)号：US06734088B1

公开(公告)日：2004-05-11

申请号：US09661536

申请日：2000-09-14

申请人： Matthew Purdy ,  Scott G. Bushman ,  James H. Hussey, Jr. ,  Douglas J. Bonser

发明人： Matthew Purdy ,  Scott G. Bushman ,  James H. Hussey, Jr. ,  Douglas J. Bonser

IPC分类号： H01L213205

CPC分类号： H01L22/20 ,  H01L21/28035

摘要： The present invention is directed to a method of controlling an etching process used to form a gate electrode on a semiconductor device. In one embodiment, the method comprises forming a layer of silicon dioxide above a semiconducting substrate, and forming a layer of polysilicon above the layer of silicon dioxide. The method further comprises sensing a thickness of the layer of polysilicon and adjusting, based upon the sensed thickness of said layer of polysilicon, at least one parameter of an etching process to be performed on said layer of polysilicon to define a gate electrode of a transistor, said etching process comprised of at least a timed etch process and an endpoint etch process.

摘要翻译： 本发明涉及一种控制用于在半导体器件上形成栅电极的蚀刻工艺的方法。 在一个实施例中，该方法包括在半导体衬底上形成二氧化硅层，并在二氧化硅层之上形成多晶硅层。 该方法还包括感测多晶硅层的厚度，并且基于感测到的所述多晶硅层的厚度调整要在​​所述多晶硅层上执行的蚀刻工艺的至少一个参数，以限定晶体管的栅电极 所述蚀刻工艺至少包括定时蚀刻工艺和端蚀刻工艺。

公开(公告)号：US20120123419A1

公开(公告)日：2012-05-17

申请号：US13291855

申请日：2011-11-08

申请人： Matthew Purdy ,  Lucile Ferrand ,  Pierric Deransart

发明人： Matthew Purdy ,  Lucile Ferrand ,  Pierric Deransart

IPC分类号： A61B17/16 ,  A61B17/17

CPC分类号： A61B17/1615 ,  A61B17/1684 ,  A61B17/1697

摘要： Embodiments of the invention include an orthopedic milling machine for preparing a glenoid bone. The milling machine uses a hub and a sleeve. The hub includes reliefs arranged to cut or mill the bone and the sleeve couples to the hub to transfer rotational motion to the hub. The hub has an axial bore sized to receive an orthopedic guide pin. The hub also has a lateral passage slot that allows the hub to move laterally towards the guide pin in order to place the guide pin within the axial bore.

摘要翻译： 本发明的实施例包括用于制备关节盂骨的矫形研磨机。 铣床使用轮毂和套筒。 轮毂包括布置成切割或研磨骨的浮雕，并且套筒耦合到轮毂以将旋转运动传递到轮毂。 轮毂具有轴向孔径，其尺寸适于接收矫形导向销。 轮毂还具有侧向通道狭槽，其允许轮毂横向地朝向引导销移动，以将引导销放置在轴向孔内。

公开(公告)号：US20050033467A1

公开(公告)日：2005-02-10

申请号：US10634013

申请日：2003-08-04

申请人： Matthew Purdy

发明人： Matthew Purdy

IPC分类号： G05B19/418 ,  H01L21/66 ,  G06F19/00

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  Y02P90/14 ,  H01L2924/00

摘要： The present invention is generally directed to various methods and systems for adaptive metrology sampling plans that may be employed to monitor various manufacturing processes. In one example, the method comprises creating a plurality of metrology sampling rules, assigning each of the metrology sampling rules a sampling weight value, identifying at least one workpiece that satisfies at least one of the metrology sampling rules, assigning the sampling weight value for each of the satisfied metrology sampling rules with the identified workpieces that satisfy the rules, and indicating a metrology operation should be performed when a cumulative total of the sampling weight values is at least equal to a pre-established trigger value. In further embodiments, the method involves indicating a metrology operation should be performed when a cumulative total of the sampling weight values for one of the metrology sampling rules is at least equal to a pre-established trigger value or indicating a metrology operation should be performed when a cumulative total of the sampling weight values for one of the workpieces is at least equal to a pre-established trigger value.

摘要翻译： 本发明一般涉及可用于监测各种制造过程的自适应测量采样计划的各种方法和系统。 在一个示例中，该方法包括创建多个度量采样规则，将每个测量采样规则分配给采样权重值，识别满足计量采样规则中的至少一个的至少一个工件，为每个 满足计量采样规则的识别工件满足规则，并且当采样权重值的累积总和至少等于预先建立的触发值时，应当执行计量操作。 在另外的实施例中，该方法包括指示当计量采样规则之一的采样权重值的累积总和至少等于预先建立的触发值或指示应当在 一个工件的采样权重值的累积总和至少等于预先建立的触发值。

公开(公告)号：US06365481B1

公开(公告)日：2002-04-02

申请号：US09660724

申请日：2000-09-13

申请人： Douglas J. Bonser ,  Matthew Purdy

发明人： Douglas J. Bonser ,  Matthew Purdy

IPC分类号： H01L2120

CPC分类号： H01L21/31116 ,  H01L28/20

摘要： Various methods of fabricating a circuit structure, such as a gate electrode or a resistor are provided. In one aspect, a method of fabricating a circuit structure is provided that includes forming a silicon structure on a substrate and forming an oxide film on the silicon structure. A first portion of the oxide film is masked while a second portion is left unmasked. The second portion of the oxide film is removed by isotropic plasma etching to expose a portion of the silicon structure, and the first portion of the oxide film is unmasked. Use of isotropic etching for removal of a resistor protect oxide reduces the potential for isolation structure damage due to aggressive overetching associated with conventional anisotropic etching techniques.

摘要翻译： 提供制造诸如栅电极或电阻器的电路结构的各种方法。 一方面，提供一种制造电路结构的方法，其包括在衬底上形成硅结构并在硅结构上形成氧化膜。 氧化膜的第一部分被掩蔽，而第二部分未被掩蔽。 通过各向同性等离子体蚀刻去除氧化膜的第二部分以暴露一部分硅结构，并且氧化膜的第一部分未被掩蔽。 使用各向同性蚀刻去除电阻保护氧化物可减少由于与常规各向异性蚀刻技术相关的侵蚀性过蚀刻而导致的隔离结构损坏的可能性。

公开(公告)号：US06245581B1

公开(公告)日：2001-06-12

申请号：US09552491

申请日：2000-04-19

申请人： Douglas Bonser ,  Anthony J. Toprac ,  Matthew Purdy ,  John R. Behnke ,  James H. Hussey, Jr.

发明人： Douglas Bonser ,  Anthony J. Toprac ,  Matthew Purdy ,  John R. Behnke ,  James H. Hussey, Jr.

IPC分类号： H01L2100

CPC分类号： H01L21/67276 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides for a method and an apparatus for controlling critical dimensions. At least one run of semiconductor devices is processed. A critical dimension measurement is performed upon at least one of the processed semiconductor device. An analysis of the critical dimension measurement is performed. A secondary process upon the semiconductor device in response to the critical dimension analysis is performed.

摘要翻译： 本发明提供了一种用于控制关键尺寸的方法和装置。 至少运行一半的半导体器件被处理。 对所处理的半导体器件中的至少一个进行临界尺寸测量。 执行关键尺寸测量的分析。 执行响应于临界尺寸分析的半导体器件上的二次工艺。