公开(公告)号：US06734088B1

公开(公告)日：2004-05-11

申请号：US09661536

申请日：2000-09-14

申请人： Matthew Purdy ,  Scott G. Bushman ,  James H. Hussey, Jr. ,  Douglas J. Bonser

发明人： Matthew Purdy ,  Scott G. Bushman ,  James H. Hussey, Jr. ,  Douglas J. Bonser

IPC分类号： H01L213205

CPC分类号： H01L22/20 ,  H01L21/28035

摘要： The present invention is directed to a method of controlling an etching process used to form a gate electrode on a semiconductor device. In one embodiment, the method comprises forming a layer of silicon dioxide above a semiconducting substrate, and forming a layer of polysilicon above the layer of silicon dioxide. The method further comprises sensing a thickness of the layer of polysilicon and adjusting, based upon the sensed thickness of said layer of polysilicon, at least one parameter of an etching process to be performed on said layer of polysilicon to define a gate electrode of a transistor, said etching process comprised of at least a timed etch process and an endpoint etch process.

摘要翻译： 本发明涉及一种控制用于在半导体器件上形成栅电极的蚀刻工艺的方法。 在一个实施例中，该方法包括在半导体衬底上形成二氧化硅层，并在二氧化硅层之上形成多晶硅层。 该方法还包括感测多晶硅层的厚度，并且基于感测到的所述多晶硅层的厚度调整要在​​所述多晶硅层上执行的蚀刻工艺的至少一个参数，以限定晶体管的栅电极 所述蚀刻工艺至少包括定时蚀刻工艺和端蚀刻工艺。

公开(公告)号：US06555397B1

公开(公告)日：2003-04-29

申请号：US09660723

申请日：2000-09-13

申请人： Douglas J. Bonser ,  Matthew Purdy ,  James H. Hussey, Jr.

发明人： Douglas J. Bonser ,  Matthew Purdy ,  James H. Hussey, Jr.

IPC分类号： H01L2128

CPC分类号： H01L21/28123 ,  Y10S438/952

摘要： Various methods of fabricating a conductor structure are provided. In one aspect, a method of fabricating a conductor structure on a first workpiece is provided. A silicon film is formed on the first workpiece. An anti-reflective coating is formed on the silicon film. A mask is formed on a first portion of the anti-reflective coating, while a second portion thereof is left unmasked. The second portion of the anti-reflective coating and the silicon film are etched. The mask is removed, and the anti-reflective coating is removed by isotropic plasma etching. Use of isotropic etching for anti-reflective coating removal eliminates thermal shock associated with heated acid bath anti-reflective coating removal.

摘要翻译： 提供制造导体结构的各种方法。 一方面，提供了在第一工件上制造导体结构的方法。 在第一工件上形成硅膜。 在硅膜上形成抗反射涂层。 掩模形成在防反射涂层的第一部分上，而其第二部分未被掩蔽。 抗反射涂层和硅膜的第二部分被蚀刻。 除去掩模，并通过各向同性等离子体蚀刻除去抗反射涂层。 使用各向同性蚀刻进行抗反射涂层去除消除了与加热的酸浴反射涂层去除相关的热冲击。

公开(公告)号：US06365481B1

公开(公告)日：2002-04-02

申请号：US09660724

申请日：2000-09-13

申请人： Douglas J. Bonser ,  Matthew Purdy

发明人： Douglas J. Bonser ,  Matthew Purdy

IPC分类号： H01L2120

CPC分类号： H01L21/31116 ,  H01L28/20

摘要： Various methods of fabricating a circuit structure, such as a gate electrode or a resistor are provided. In one aspect, a method of fabricating a circuit structure is provided that includes forming a silicon structure on a substrate and forming an oxide film on the silicon structure. A first portion of the oxide film is masked while a second portion is left unmasked. The second portion of the oxide film is removed by isotropic plasma etching to expose a portion of the silicon structure, and the first portion of the oxide film is unmasked. Use of isotropic etching for removal of a resistor protect oxide reduces the potential for isolation structure damage due to aggressive overetching associated with conventional anisotropic etching techniques.

摘要翻译： 提供制造诸如栅电极或电阻器的电路结构的各种方法。 一方面，提供一种制造电路结构的方法，其包括在衬底上形成硅结构并在硅结构上形成氧化膜。 氧化膜的第一部分被掩蔽，而第二部分未被掩蔽。 通过各向同性等离子体蚀刻去除氧化膜的第二部分以暴露一部分硅结构，并且氧化膜的第一部分未被掩蔽。 使用各向同性蚀刻去除电阻保护氧化物可减少由于与常规各向异性蚀刻技术相关的侵蚀性过蚀刻而导致的隔离结构损坏的可能性。

公开(公告)号：US06812077B1

公开(公告)日：2004-11-02

申请号：US10299433

申请日：2002-11-19

申请人： Darin Chan ,  Douglas J. Bonser ,  Mark S. Chang

发明人： Darin Chan ,  Douglas J. Bonser ,  Mark S. Chang

IPC分类号： H01L2100

CPC分类号： H01L21/32105 ,  H01L21/28088 ,  H01L21/28123

摘要： Patterning of a gate line is terminated prior to etching completely through the conductive layer from which it is patterned. Surfaces of the conductive layer are then reacted in a reactive atmosphere, and the reacted surfaces are removed, creating a narrow gate line. The protection provided by the remaining portion of the conductive layer during reaction protects the lower corners of the patterned feature from undercutting growth of reacted material. Alternatively, a gate line is patterned from a multi-layered conductive structure that includes a lower conductive layer and an upper conductive layer that exhibits higher reactivity in a reactive atmosphere than the lower layer. The upper layer is patterned and then the structure is reacted in the reactive atmosphere. Reacted portions of the upper layer are then removed and the lower layer is patterned in a self-aligned manner to complete the formation of a gate line and gate insulator.

摘要翻译： 在蚀刻完全通过图案化的导电层之前终止栅极线的图案化。 然后在反应性气氛中使导电层的表面反应，除去反应的表面，产生窄的栅极线。 在反应期间由导电层的剩余部分提供的保护保护图案化特征的下角部不被反应材料的底切生长。 或者，栅极线从包括下导电层和上导电层的多层导电结构图案化，反应性气氛中的反应性比下层高。 上层被图案化，然后结构在反应性气氛中反应。 然后去除上层的反应部分，并且以自对准方式图案化下层，以完成栅极线和栅极绝缘体的形成。

公开(公告)号：US06750127B1

公开(公告)日：2004-06-15

申请号：US10367407

申请日：2003-02-14

申请人： Mark S. Chang ,  Darin Chan ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser

发明人： Mark S. Chang ,  Darin Chan ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser

IPC分类号： H01L213205

CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/0337

摘要： An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides improved pattern transfer accuracy compared to conventional undoped amorphous carbon.

摘要翻译： 注入一个或多个掺杂剂的无定形碳层，其增强无定形碳对通常用于蚀刻多晶硅的蚀刻剂如氯和HBr的蚀刻电阻率。 这样的层可以被图案化以形成用于蚀刻多晶硅的手掩模，其与常规未掺杂的无定形碳相比提供改进的图案转印精度。

公开(公告)号：US06900139B1

公开(公告)日：2005-05-31

申请号：US10135175

申请日：2002-04-30

申请人： Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser ,  Karen Turnquest

发明人： Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser ,  Karen Turnquest

IPC分类号： H01L21/311 ,  H01L21/3213 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/31138 ,  H01L21/32139 ,  H01L21/76838

摘要： A method for forming semiconductor features, e.g., gates, line widths, thicknesses and spaces, produced by a photoresist trim procedure, in a closed loop process is presented. The methodology enables the use of optical emission spectroscopy and/or optical interferometry techniques for endpoint monitoring during resist trim etching of photoresist structures. Various types of material layers underlying photoresist structures are employed in order to provide an endpoint signal to enable closed loop control, with resultant improved targeting of photoresist mask and reproducibility. In addition, the method provides for in situ etch rate monitoring, and is not adversely affected by etch rate variances within an etching chamber during an etch process.

摘要翻译： 提出了一种用于在闭环过程中形成由光致抗蚀剂修整过程产生的半导体特征（例如栅极，线宽，厚度和空间）的方法。 该方法使得能够在抗蚀剂修饰蚀刻光致抗蚀剂结构期间使用光发射光谱学和/或光学干涉测量技术来进行端点监测。 采用各种类型的光致抗蚀剂结构下面的材料层，以提供端点信号以实现闭环控制，从而改善光致抗蚀剂掩模的靶向性和再现性。 此外，该方法提供了原位蚀刻速率监测，并且不会在蚀刻工艺期间蚀刻室内的蚀刻速率变化受到不利影响。

公开(公告)号：US06797552B1

公开(公告)日：2004-09-28

申请号：US10299434

申请日：2002-11-19

申请人： Mark S. Chang ,  Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy

发明人： Mark S. Chang ,  Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L21336

CPC分类号： H01L21/823456 ,  H01L21/0332 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139

摘要： A layer of material is patterned anisotropically using a bi-layer hardmask structure. Residual photoresist from a photoresist mask used to pattern an upper layer of the bi-layer hardmask is removed prior to patterning of the polysilicon layer. Passivation agents are later introduced from an external source during patterning of the layer of material. This provides a substantially uniform supply of passivation agents to all parts of the layer of material as it is being etched, rather than relying on the generation of passivation agents from consumption of photoresist during etching, which can produce local non-uniformities of passivation agent availability owing to differences in photoresist thickness remaining on different sized features.

摘要翻译： 使用双层硬掩模结构各向异性地图案化材料层。 在用于图案化双层硬掩模的上层的光致抗蚀剂掩模的残余光致抗蚀剂在图案化多晶硅层之前被去除。 在图案化材料层之后，钝化剂随后从外部源引入。 这提供了当被蚀刻时材料层的所有部分基本上均匀地供应钝化剂，而不是依赖于在蚀刻期间消除光致抗蚀剂的钝化剂的产生，这可以产生钝化剂可用性的局部不均匀性 由于在不同尺寸的特征上残留的光刻胶厚度的差异。

公开(公告)号：US5504328A

公开(公告)日：1996-04-02

申请号：US352579

申请日：1994-12-09

申请人： Douglas J. Bonser

发明人： Douglas J. Bonser

IPC分类号： H01J49/16 ,  H01J49/00

CPC分类号： H01J49/16

摘要： An apparatus and method for detecting the endpoint of an etch during semiconductor fabrication is provided. The endpoint detection system utilizes a mass spectrometer having an energy source located outside the vacuum chamber of the endpoint detection system, thus providing an easily replaceable energy source. The energy source may be a light source to provide photo-ionization. The energy source may be selected based upon the gas species of the etch of which an endpoint as being detected. The energy is directed into an ionization chamber of the endpoint detection system through a transparent window.

摘要翻译： 提供了一种用于在半导体制造期间检测蚀刻的端点的装置和方法。 端点检测系统利用具有位于端点检测系统的真空室外部的能量源的质谱仪，从而提供容易替换的能量源。 能量源可以是提供光电离的光源。 能量源可以基于被检测到的端点的蚀刻的气体种类来选择。 能量通过透明窗口引导到端点检测系统的电离室。

公开(公告)号：US20100267237A1

公开(公告)日：2010-10-21

申请号：US12426824

申请日：2009-04-20

申请人： Douglas J. Bonser ,  Frank S. Johnson ,  Catherine B. Labelle

发明人： Douglas J. Bonser ,  Frank S. Johnson ,  Catherine B. Labelle

IPC分类号： H01L21/308

CPC分类号： H01L21/3086 ,  H01L29/66795

摘要： Methods are provided for fabricating a semiconductor device on and in a semiconductor substrate. In accordance with an exemplary embodiment of the invention, one method comprises forming a sacrificial mandrel overlying the substrate, the sacrificial mandrel having sidewalls. Sidewall spacers are formed adjacent the sidewalls of the sacrificial mandrel. The sacrificial mandrel is removed using an ashing process, and the substrate is etched using the sidewall spacers as an etch mask after removal of the sacrificial mandrel.

摘要翻译： 提供了用于在半导体衬底上和半导体衬底中制造半导体器件的方法。 根据本发明的示例性实施例，一种方法包括形成覆盖在基底上的牺牲心轴，牺牲心轴具有侧壁。 侧壁间隔件邻近牺牲心轴的侧壁形成。 使用灰化处理去除牺牲心轴，并且在去除牺牲心轴之后，使用侧壁间隔物作为蚀刻掩模蚀刻衬底。

公开(公告)号：US06913958B1

公开(公告)日：2005-07-05

申请号：US10366800

申请日：2003-02-14

申请人： Marina V. Plat ,  Marilyn I. Wright ,  Chih Yuh Yang ,  Douglas J. Bonser

发明人： Marina V. Plat ,  Marilyn I. Wright ,  Chih Yuh Yang ,  Douglas J. Bonser

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/302 ,  H01L21/3205 ,  H01L21/84

CPC分类号： H01L21/0332 ,  H01L21/0337 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32139

摘要： In the formation of a semiconductor device, one or more hardmasks are formed during a process for patterning a device feature. One or more of the hardmasks is subjected to an isotropic etch to trim the hardmask prior to patterning an underlying layer. The trimmed hardmask layer is preferably an amorphous carbon layer.

摘要翻译： 在形成半导体器件时，在用于图案化器件特征的工艺期间形成一个或多个硬掩模。 对一个或多个硬掩模进行各向同性蚀刻，以在图案化底层之前对硬掩模进行修整。 修整的硬掩模层优选为无定形碳层。