-
公开(公告)号：US20100085828A1
公开(公告)日：2010-04-08
申请号：US12247235
申请日：2008-10-08
CPC分类号： G11C8/08 , G11C5/145 , G11C11/4085
摘要： A method for reducing leakage current of a memory device includes supplying a first voltage to a main wordline driver, supplying a second voltage greater than the first voltage to a local wordline driver, and employing a transistor in the local wordline driver with a threshold voltage greater than a specific value.
摘要翻译： 一种用于减小存储器件泄漏电流的方法包括向主字线驱动器提供第一电压，向本地字线驱动器提供大于第一电压的第二电压，以及在本地字线驱动器中采用阈值电压较大的晶体管 比具体值。
-
公开(公告)号：US08269550B2
公开(公告)日：2012-09-18
申请号：US12610369
申请日：2009-11-02
CPC分类号： G05F1/567
摘要： A reference voltage generation circuit for generating a reference voltage that can adaptively depend on temperature and process includes: a comparator, having a process, temperature and voltage (PVT) insensitive reference as a first input, and a feedback of the output as a second input, for generating a voltage reference output; a first resistor, coupled to the output of the operational amplifier; a second and a third variable resistor coupled in parallel, and coupled between the first resistor and ground; and a transistor, coupled between the third variable resistor and ground.
摘要翻译： 用于产生可以自适应地依赖于温度和过程的参考电压的参考电压产生电路包括：具有作为第一输入的过程，温度和电压（PVT）不敏感参考值的比较器，以及输出作为第二输入的反馈 ，用于产生电压参考输出; 耦合到运算放大器的输出的第一电阻器; 并联耦合的第二和第三可变电阻器，并且耦合在第一电阻器和地之间; 以及耦合在第三可变电阻器和地之间的晶体管。
-
公开(公告)号：US07876612B2
公开(公告)日：2011-01-25
申请号：US12247235
申请日：2008-10-08
IPC分类号： G11C16/04
CPC分类号： G11C8/08 , G11C5/145 , G11C11/4085
摘要： A method for reducing leakage current of a memory device includes supplying a first voltage to a main wordline driver, supplying a second voltage greater than the first voltage to a local wordline driver, and employing a transistor in the local wordline driver with a threshold voltage greater than a specific value.
摘要翻译： 一种用于减小存储器件泄漏电流的方法包括向主字线驱动器提供第一电压，向本地字线驱动器提供大于第一电压的第二电压，以及在本地字线驱动器中采用阈值电压较大的晶体管 比具体值。
-
公开(公告)号：US20110102057A1
公开(公告)日：2011-05-05
申请号：US12610369
申请日：2009-11-02
IPC分类号： H01L37/00
CPC分类号： G05F1/567
摘要： A reference voltage generation circuit for generating a reference voltage that can adaptively depend on temperature and process includes: a comparator, having a process, temperature and voltage (PVT) insensitive reference as a first input, and a feedback of the output as a second input, for generating a voltage reference output; a first resistor, coupled to the output of the operational amplifier; a second and a third variable resistor coupled in parallel, and coupled between the first resistor and ground; and a transistor, coupled between the third variable resistor and ground.
摘要翻译： 用于产生可以自适应地依赖于温度和过程的参考电压的参考电压产生电路包括：具有作为第一输入的过程，温度和电压（PVT）不敏感参考值的比较器，以及作为第二输入的输出的反馈 ，用于产生电压参考输出; 耦合到运算放大器的输出的第一电阻器; 并联耦合的第二和第三可变电阻器，并且耦合在第一电阻器和地之间; 以及耦合在第三可变电阻器和地之间的晶体管。
-
5.发明授权Method for reducing power consumption in a volatile memory and related device 有权用于降低易失性存储器和相关设备中的功耗的方法公开(公告)号：US07813209B2
公开(公告)日：2010-10-12
申请号：US12243944
申请日：2008-10-01
CPC分类号： G11C11/4094 , G11C5/063 , G11C7/08 , G11C7/12 , G11C11/4074 , G11C11/4091
摘要： A method for reducing power consumption in a volatile memory includes switching off a bitline voltage provider according to a leakage control signal when a bitline array corresponding to the bitline voltage provider is dysfunctional due to a wordline to bitline short, controlling connections between a plurality of first bitline arrays corresponding to the bitline voltage provider and a plurality of sense amplifiers according to an access control signal, controlling connections between a plurality of second bitline arrays corresponding to the plurality of first bitline arrays and the plurality of sense amplifiers according to the access control signal, and providing power to the plurality of corresponding sense amplifiers according to the access control signal.
摘要翻译： 一种用于降低易失性存储器中的功耗的方法，包括当与位线电压提供器相对应的位线阵列由于字线到位线短而失效时，根据泄漏控制信号来切断位线电压提供器，控制多个第一 根据访问控制信号对应于位线电压提供者的位线阵列和多个读出放大器，根据访问控制信号控制对应于多个第一位线阵列的多个第二位线阵列与多个读出放大器之间的连接 并且根据访问控制信号向多个对应的读出放大器提供电力。
-
公开(公告)号：US06343044B1
公开(公告)日：2002-01-29
申请号：US09679124
申请日：2000-10-04
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C5/146 , G11C8/08 , G11C11/4074 , G11C2207/104
摘要： A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.
摘要翻译： 用于实现Vbb（阵列体偏置）和Vwl（负字线）电压发生器的存储电路中的功耗的显着降低的系统和方法。 该系统包括在睡眠或待机模式期间关闭负WL发生器，使得不消耗电力。 执行松弛的刷新操作，负的WL由Vbb发生器供电。 由于联合Vbb-Vwl去耦方案，耦合到BL摆幅的负WL电源的噪声减小。 在活动模式下，Vbb和Vneg被分离，以避免任何交叉噪声并保持设计灵活性。 在上电期间，Vwl发生器提高了Vbb电平的上升速率。 其优点可概括为：（1）Vbb发电机设计更简单，（2）Vbb发电机尺寸小得多，（3）Vbb功率降低，（4）Vwl发电机无待机电流，（5）低去耦噪声 待机或休眠模式下的Vwl电平，（6）上电期间Vbb的提升速率，（7）在活动模式期间Vbb和Vwl之间没有交叉噪声，（8）Vbb和Vbb的设计灵活性 Vwl处于活动模式。 本发明的原理和优点可以应用于任何两个或多个DC发电机系统，负极或正极。
-
公开(公告)号：US08102690B2
公开(公告)日：2012-01-24
申请号：US12577704
申请日：2009-10-12
CPC分类号： G11C7/1018 , G11C5/025 , G11C7/1045 , G11C2207/105
摘要： A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the center of the DDR3 chip; and an array of banks, each bank having a specific logical address, surrounding the pads. The chip system further includes: a clock, coupled to the DDR3 chip, for controlling a rate of data transmission; and a memory controller, coupled to the clock, for coordinating transmitted data with relevant processes, and for selectively reassigning the bank logical addresses according to a specific operational mode.
摘要翻译： 在特定操作模式下降低功耗的芯片系统包括：DDR3芯片，包括：设置在DDR3芯片中心的多个焊盘; 和一组银行，每个银行都有一个特定的逻辑地址，围绕着这些垫。 芯片系统还包括：耦合到DDR3芯片的时钟，用于控制数据传输速率; 以及存储器控制器，其耦合到时钟，用于根据特定操作模式来协调与相关过程的传输数据，并且用于选择性地重新分配存储体逻辑地址。
-
8.发明授权DRAM positive wordline voltage compensation device for array device threshold voltage and voltage compensating method thereof 有权用于阵列器件阈值电压及其电压补偿方法的DRAM正字线电压补偿装置公开(公告)号：US07940549B2
公开(公告)日：2011-05-10
申请号：US12573486
申请日：2009-10-05
IPC分类号： G11C11/24
CPC分类号： G11C11/4085 , G11C8/08 , G11C11/4074
摘要： The configurations of a DRAM positive wordline voltage compensation device and a voltage compensating method thereof are provided in the present invention. The proposed device includes a comparator having a first input terminal receiving a positive wordline voltage feedback signal, a second input terminal receiving a compensating reference of array device threshold voltage and an output terminal generating a first enable signal, an oscillator receiving the first enable signal and generating an oscillating signal when the first enable signal is active and a charge pump having a first input terminal receiving a second enable signal, a second input terminal receiving the oscillating signal and an output terminal generating a positive wordline voltage being a sum of a bitline high voltage, an array device threshold voltage and a voltage margin.
摘要翻译： 在本发明中提供了DRAM正字线电压补偿装置及其电压补偿方法的结构。 所提出的装置包括比较器，其具有接收正字线电压反馈信号的第一输入端，接收阵列器件阈值电压的补偿参考的第二输入端和产生第一使能信号的输出端，接收第一使能信号的振荡器和 当所述第一使能信号有效时产生振荡信号，以及具有接收第二使能信号的第一输入端的电荷泵，接收所述振荡信号的第二输入端子以及产生正字线电压的输出端子，所述正极线电压是位线高 电压，阵列器件阈值电压和电压裕度。
-
公开(公告)号：US20110085402A1
公开(公告)日：2011-04-14
申请号：US12577704
申请日：2009-10-12
CPC分类号： G11C7/1018 , G11C5/025 , G11C7/1045 , G11C2207/105
摘要： A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the centre of the DDR3 chip; and an array of banks, each bank having a specific logical address, surrounding the pads. The chip system further includes: a clock, coupled to the DDR3 chip, for controlling a rate of data transmission; and a memory controller, coupled to the clock, for coordinating transmitted data with relevant processes, and for selectively reassigning the bank logical addresses according to a specific operational mode.
摘要翻译： 在特定操作模式下降低功耗的芯片系统包括：DDR3芯片，包括：设置在DDR3芯片中心的多个焊盘; 和一组银行，每个银行都有一个特定的逻辑地址，围绕着这些垫。 芯片系统还包括：耦合到DDR3芯片的时钟，用于控制数据传输速率; 以及存储器控制器，其耦合到时钟，用于根据特定操作模式来协调与相关过程的传输数据，并且用于选择性地重新分配存储体逻辑地址。
-
10.发明申请公开(公告)号：US20100080070A1
公开(公告)日：2010-04-01
申请号：US12243944
申请日：2008-10-01
CPC分类号： G11C11/4094 , G11C5/063 , G11C7/08 , G11C7/12 , G11C11/4074 , G11C11/4091
摘要： A method for reducing power consumption in a volatile memory includes switching off a bitline voltage provider according to a leakage control signal when a bitline array corresponding to the bitline voltage provider is dysfunctional due to a wordline to bitline short, controlling connections between a plurality of first bitline arrays corresponding to the bitline voltage provider and a plurality of sense amplifiers according to an access control signal, controlling connections between a plurality of second bitline arrays corresponding to the plurality of first bitline arrays and the plurality of sense amplifiers according to the access control signal, and providing power to the plurality of corresponding sense amplifiers according to the access control signal.
摘要翻译： 一种用于降低易失性存储器中的功耗的方法，包括当与位线电压提供器相对应的位线阵列由于字线到位线短而失效时，根据泄漏控制信号来切断位线电压提供器，控制多个第一 根据访问控制信号对应于位线电压提供者的位线阵列和多个读出放大器，根据访问控制信号控制对应于多个第一位线阵列的多个第二位线阵列与多个读出放大器之间的连接 并且根据访问控制信号向多个对应的读出放大器提供电力。
-
-
-
-
-
-
-
-
-
搜索结果
11 条记录 (耗时 0.014 秒)
