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公开(公告)号：US07797681B2
公开(公告)日：2010-09-14
申请号：US11431926
申请日：2006-05-11
IPC分类号： G06F9/44
CPC分类号： G06F9/4812 , G06F9/3861 , G06F9/462
摘要： A data processor 2 has privilege levels associated with it including a user level and a privileged level. The processor 2 also has multiple stack memories which can be used including one or more process stacks, a main stack and a deep stack. The stack memory to be used is de-coupled from the privilege level. An activation level state variable tracking the number of pending exceptions is held by the processor and used to modify which stack memory stores pending state values when an exception occurs. If the system is at a base level of activation, corresponding to currently no pending exceptions, then when an exception occurs the current state data is saved on the process stack with the main stack being available for the exception handling code. Particular exceptions can be flagged as requiring use of a deep stack rather than either the process stack or the main stack. If the system is not at the base level of activation, then the main stack is used to save state variables when an exception occurs rather than the process stack.
摘要翻译： 数据处理器2具有与其相关联的特权级别，其包括用户级别和特权级别。 处理器2还具有可以使用的多个堆栈存储器，包括一个或多个处理堆栈，主堆栈和深堆栈。 要使用的堆栈内存从特权级别去耦合。 跟踪待处理异常的数量的激活级状态变量由处理器保存，并用于修改哪个堆栈存储器在发生异常时存储待处理的状态值。 如果系统处于激活的基本级别，对应于当前没有挂起的异常，则当发生异常时，当前状态数据保存在进程堆栈中，主堆栈可用于异常处理代码。 可以将特殊异常标记为需要使用深栈，而不是使用进程堆栈或主堆栈。 如果系统不在激活的基本级别，则主堆栈用于在异常发生时保存状态变量而不是进程堆栈。
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公开(公告)号：US07401210B2
公开(公告)日：2008-07-15
申请号：US11092984
申请日：2005-03-30
IPC分类号： G06F9/00
CPC分类号： G06F9/3016 , G06F9/30054 , G06F9/322 , G06F9/4486
摘要： Following execution of a subroutine, a return instruction is executed having an address as an input operand thereto. This input operand is compared with one or more predetermined values to detect a match and the return instruction response is selected in dependence upon whether or not a match is detected. Thus, the return address value can be used to invoke differing return instruction responses, such as an exception return response or a procedure return response. The one or more predetermined addresses may be conveniently allocated to the highest memory addresses within the memory map.
摘要翻译： 在执行子程序之后，执行具有作为其输入操作数的地址的返回指令。 将该输入操作数与一个或多个预定值进行比较以检测匹配，并且根据是否检测到匹配来选择返回指令响应。 因此，返回地址值可以用于调用不同的返回指令响应，例如异常返回响应或过程返回响应。 可以方便地将一个或多个预定地址分配给存储器映射内的最高存储器地址。
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公开(公告)号：US07068545B1
公开(公告)日：2006-06-27
申请号：US11028501
申请日：2005-01-04
IPC分类号： G11C7/00
CPC分类号： G06F12/1441
摘要： A data processor (100) has a memory operable to store data values; a memory protection unit (130) operable to associate memory attributes with portions of said memory and to identify a plurality of memory regions corresponding to respective address ranges of said memory. The memory protection unit is operable to associate with at least one of the plurality of memory regions (150) a respective memory region specifier comprising an attributes field (230) for defining a set of memory attributes associated with said memory region and a sub-region field (240) for holding a sub-region membership value. The sub-region membership value specifies, for each of a plurality of sub-regions of the memory region, whether respective sub-regions (160-1 to 160-8) are member sub-regions or non-member sub-regions such that said memory attributes are applied to said member sub-regions but are not applied to said non-member sub-regions.
摘要翻译： 数据处理器（100）具有可操作以存储数据值的存储器; 存储器保护单元（130），其可操作以将存储器属性与所述存储器的部分相关联，并且识别对应于所述存储器的相应地址范围的多个存储器区域。 存储器保护单元可操作以将多个存储器区域（150）中的至少一个与相应的存储器区域说明符相关联，该存储器区域说明符包括用于定义与所述存储器区域相关联的一组存储器属性的属性字段（230）和子区域 用于保存子区域成员值的字段（240）。 子区域成员关系值针对存储区域的多个子区域中的每一个指定各个子区域（160-1至160-8）是否是成员子区域或非成员子区域，使得 所述存储器属性被应用于所述成员子区域，但不应用于所述非成员子区域。
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4.发明授权Performing diagnostic operations upon a data processing apparatus with power down support 有权对具有断电支持的数据处理设备执行诊断操作公开(公告)号：US07228457B2
公开(公告)日：2007-06-05
申请号：US10801131
申请日：2004-03-16
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： A system-on-chip integrated circuit 2 is provided with multiple data processing circuits 4, 6, 8 each with an associated diagnostic interface circuit 16, 18, 20 connected via a diagnostic transaction bus 14 to a diagnostic transaction master circuit 12. The diagnostic master transaction circuit 12 issues diagnostic transaction requests to the diagnostic interface circuits 16, 18, 20. If the associated data processing circuits 4, 6, 8 are powered-down, or otherwise non responsive, then the diagnostic interface circuit 16, 18, 20 returns a diagnostic bus transaction error signal to the diagnostic transaction master circuit 12. A sticky-bit latch 30 within each diagnostic interface circuit 16, 18, 20 serves to record a power-down event and force generation of the diagnostic bus transaction error signal until that sticky bit is cleared by the diagnostic mechanisms. This ensure the diagnostic mechanisms are made aware of the power-down event so they may take any appropriate remedial action that might be necessary as a result of that power-down event.
摘要翻译： 系统级芯片集成电路2具有多个数据处理电路4,6,8，每个数据处理电路具有通过诊断事务总线14连接到诊断事务主电路12的相关联的诊断接口电路16,18,20。 诊断主交易电路12向诊断接口电路16,18,20发出诊断事务请求。 如果相关联的数据处理电路4,6,8被断电或以其他方式不响应，则诊断接口电路16,18,20将诊断总线事务错误信号返回给诊断事务主电路12。 每个诊断接口电路16,18,20内的粘滞锁存器30用于记录诊断总线事务错误信号的掉电事件和强制产生，直到诊断机构清除该粘滞位。 这样可以确保诊断机制能够意识到掉电事件，因此可能会由于断电事件而采取任何必要的补救措施。
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公开(公告)号：US07805550B2
公开(公告)日：2010-09-28
申请号：US11032226
申请日：2005-01-11
CPC分类号： G06F13/24 , G06F1/3228
摘要： A data processing apparatus and method are provided for managing polling loops. The data processing apparatus comprises a main processing unit and a subsidiary processing unit operable to perform a task on behalf of the main processing unit. The subsidiary processing unit is operable to set a completion field when the task has been completed and the main processing unit is operable to poll the completion field in order to determine whether the task has been completed. If on polling the completion field a threshold number of times the main processing unit determines that the task has not been completed, the main processing unit is operable to enter a power saving mode. The subsidiary processing unit is operable, when the task has been completed, to cause a notification to be issued on a path interconnecting the main processing unit and the subsidiary processing unit. The main processing unit is arranged, upon receipt of the notification to exit the power saving mode. This provides a particularly efficient technique for managing a polling loop within the data processing apparatus.
摘要翻译： 提供了一种用于管理轮询循环的数据处理装置和方法。 数据处理装置包括主处理单元和辅助处理单元，可操作以代表主处理单元执行任务。 辅助处理单元可操作以在任务完成时设置完成字段，并且主处理单元可操作地轮询完成字段以便确定任务是否已经完成。 如果在轮询完成字段时，主处理单元确定任务尚未完成的阈值次数，则主处理单元可操作以进入省电模式。 当完成任务时，辅助处理单元可操作地在连接主处理单元和辅助处理单元的路径上发出通知。 主处理单元在接收到退出省电模式的通知时被布置。 这提供了一种用于管理数据处理装置内的轮询循环的特别有效的技术。
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公开(公告)号：US07426659B2
公开(公告)日：2008-09-16
申请号：US11085263
申请日：2005-03-22
IPC分类号： G06F11/00
CPC分类号： G06F11/079 , G06F11/2733
摘要： A data processing system 2 is described having a central processing unit 4 and a diagnostic mechanism 10. The central processing unit 4 is switchable into a power-down mode from which it may resume into a normal operation mode. When the central processing unit 4 resumes into the normal operation mode, execution of program instructions is inhibited by the diagnostic mechanism 10 to allow the diagnostic mechanism to be appropriately programmed such that the immediate power-up code and operations can be properly diagnosed. The requirement to prevent program instruction execution on power-up is programmed by writing to a latch 16 within the diagnostic mechanism 10 prior to the power-down. The prevention of program execution may be achieved, for example, by generation of a halt request or by extending the time period for which the central processing unit 4 is held in reset following power-up.
摘要翻译： 描述了具有中央处理单元4和诊断机构10的数据处理系统2.中央处理单元4可切换到能够恢复到正常操作模式的掉电模式。 当中央处理单元4恢复到正常操作模式时，诊断机构10禁止程序指令的执行，以允许对诊断机构进行适当的编程，使得立即上电代码和操作能被正确诊断。 通过在断电之前写入诊断机构10内的锁存器16来编程防止上电时程序指令执行的要求。 程序执行的防止可以例如通过产生停止请求或通过在上电之后将中央处理单元4保持在复位的时间段来实现。
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公开(公告)号：US20120131312A1
公开(公告)日：2012-05-24
申请号：US13137948
申请日：2011-09-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F7/764 , G06F7/768 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/3887
摘要： A data processing apparatus 2 comprises a processing circuit 4 and instruction decoder 6. A bitfield manipulation instruction controls the processing apparatus 2 to generate at least one result data element from corresponding first and second source data elements src1, src2. Each result data element includes a portion corresponding to a bitfield bf of the corresponding first source data element src1. Bits of the result data element that are more significant than the inserted bitfield bf have a prefix value p that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element src2, and a third prefix value corresponding to a sign extension of the bitfield bf of the first source data element src1.
摘要翻译： 数据处理装置2包括处理电路4和指令解码器6.位
域操作指令控制处理装置2，从对应的第一和第二源数据元素src1，src2生成至少一个结果数据元素。 每个结果数据元素包括对应于相应的第一源数据元素src1的位字段bf的部分。 比插入的位字段bf更重要的结果数据元素的位具有基于由指令指定的控制值被选择的前缀值p作为具有零值的第一前缀值，第二前缀值 具有相应的第二源数据元素src2的一部分的值，以及与第一源数据元素src1的位域bf的符号扩展对应的第三前缀值。-
公开(公告)号：US07206884B2
公开(公告)日：2007-04-17
申请号：US10775334
申请日：2004-02-11
IPC分类号： G06F13/26
CPC分类号： G06F9/4818
摘要： A data processing system 2 having a nested interrupt controller 24 supports nested active interrupts. The priority levels associated with different interrupts are alterable (possibly programmable) whilst the system is running. In order to prevent problems associated with priority inversions within nested interrupts, the nested interrupt controller when considering whether a pending interrupt should pre-empt existing active interrupts, compares the priority of the pending interrupt with the highest priority of any of the currently active interrupts that are nested together.
摘要翻译： 具有嵌套中断控制器24的数据处理系统2支持嵌套的活动中断。 与系统正在运行时，与不同中断关联的优先级别是可改变的（可能是可编程的）。 为了防止在嵌套中断中与优先级颠倒相关的问题，嵌套中断控制器在考虑暂挂中断是否应该预先占用现有的活动中断时，将待处理中断的优先级与任何当前活动中断的最高优先级进行比较， 嵌套在一起
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公开(公告)号：US09804851B2
公开(公告)日：2017-10-31
申请号：US13064257
申请日：2011-03-14
申请人： Richard Roy Grisenthwaite , David James Seal , Philippe Jean-Pierre Raphalen , Lee Douglas Smith
发明人： Richard Roy Grisenthwaite , David James Seal , Philippe Jean-Pierre Raphalen , Lee Douglas Smith
CPC分类号： G06F9/3016 , G06F9/3001 , G06F9/30112 , G06F9/3861 , G06F21/577 , G06F21/70 , G06F2221/2145
摘要： A data processing system is provided with processing circuitry as well as a bank of 64-bit registers. An instruction decoder decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers. The instruction decoder is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands where all of the operands are 64-bit operands or all of the operands are 32-bit operands. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.
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公开(公告)号：US09092215B2
公开(公告)日：2015-07-28
申请号：US12929865
申请日：2011-02-22
CPC分类号： G06F9/30112 , G06F9/30123 , G06F9/30138 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/384 , G06F9/3863
摘要： A processor 4 is provided which supports a first instruction set specifying 32-bit architectural registers and a second instruction set specifying 64-bit architectural registers. Each of these instruction sets is presented with its own set of architectural registers for use. The first set of registers presented to the first instruction set has a one-to-one mapping to the second set of registers presented to this second instruction set. The registers which are provided in hardware are 64-bit registers. In some embodiments, when executing program instructions of the first instruction set, only the least significant portion of these 64-bit registers are accessed and manipulated with the remaining most significant portion of the registers being left unaltered. Register specifying fields within instructions of the first instruction set are decoded together with a current exception mode to determine which architectural register to use whereas the second instruction set uses register specifying fields without a dependence upon exception mode to determine which architectural register are to be used.
摘要翻译： 提供处理器4，其支持指定32位架构寄存器的第一指令集和指定64位架构寄存器的第二指令集。 这些指令集中的每一个都带有自己的一组架构寄存器供使用。 呈现给第一指令集的第一组寄存器具有与呈现给该第二指令集的第二组寄存器的一对一映射。 在硬件中提供的寄存器是64位寄存器。 在一些实施例中，当执行第一指令集的程序指令时，只有这些64位寄存器的最低有效部分被访问和操作，其中最重要的寄存器部分保持不变。 在第一指令集的指令内的寄存器指定字段与当前异常模式一起被解码以确定要使用的架构寄存器，而第二指令集使用寄存器指定字段而不依赖于异常模式来确定要使用哪个架构寄存器。
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