公开(公告)号：US20140032956A1

公开(公告)日：2014-01-30

申请号：US13559320

申请日：2012-07-26

申请人： Richard V. De Caro ,  Danut Manea ,  YONGLIANG WANG ,  Stephen Trinh ,  Paul Hill

发明人： Richard V. De Caro ,  Danut Manea ,  YONGLIANG WANG ,  Stephen Trinh ,  Paul Hill

IPC分类号： G06F1/32

CPC分类号： G06F1/3296 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3275 ,  G06F1/3287 ,  G11C5/147 ,  G11C5/148 ,  G11C16/30 ,  G11C2216/30 ,  Y02D10/14 ,  Y02D50/20

摘要： A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.

摘要翻译： 存储器件包括电压调节器，其输出为存储器件的各种其他部件提供电压供应，包括命令用户界面。 存储器件通过向存储器件提供软件命令而被置于超深度掉电模式，该命令导致电压调节器的输出被禁止。 为了使存储器件脱离超深度掉电模式，芯片选择信号被提供给存储器件，其包括即使当存储器件处于超深度功率时仍保持通电的唤醒电路 降模式。 当存储器件处于超深度掉电模式时，芯片选择信号的接收使得电压调节器的输出被使能，从而为完全断电的部件提供电力。

公开(公告)号：US20110170354A1

公开(公告)日：2011-07-14

申请号：US13052810

申请日：2011-03-21

申请人： Richard V. De Caro ,  Danut Manea

发明人： Richard V. De Caro ,  Danut Manea

IPC分类号： G11C16/10 ,  G11C7/00 ,  H05K13/00

CPC分类号： G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2272 ,  Y10T29/49002

摘要： This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.

摘要翻译： 本文件还讨论了包括主机控制器，输入/输出缓冲器和存储器件的系统。 存储器设备耦合到主机控制器，并被配置为从主机控制器接收读取命令。 非易失性包括与非易失性存储器通信的接口控制逻辑。 接口控制逻辑包括耦合到非易失性存储器和输入/输出缓冲器的等待时间编程电路。 延迟编程电路在读操作期间从非易失性存储器传送数据之前存储对应于要在非易失性存储器处提供的虚拟字节延迟的至少一个值。

公开(公告)号：US07929356B2

公开(公告)日：2011-04-19

申请号：US12205518

申请日：2008-09-05

申请人： Richard V. De Caro ,  Danut Manea

发明人： Richard V. De Caro ,  Danut Manea

IPC分类号： G11C16/04

CPC分类号： G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2272 ,  Y10T29/49002

摘要： This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.

摘要翻译： 本文件还讨论了包括主机控制器，输入/输出缓冲器和存储器件的系统。 存储器设备耦合到主机控制器，并被配置为从主机控制器接收读取命令。 非易失性包括与非易失性存储器通信的接口控制逻辑。 接口控制逻辑包括耦合到非易失性存储器和输入/输出缓冲器的等待时间编程电路。 延迟编程电路在读操作期间从非易失性存储器传送数据之前存储对应于要在非易失性存储器处提供的虚拟字节延迟的至少一个值。

公开(公告)号：US20100061152A1

公开(公告)日：2010-03-11

申请号：US12205518

申请日：2008-09-05

申请人： Richard V. De Caro ,  Danut Manea

发明人： Richard V. De Caro ,  Danut Manea

IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C8/00 ,  H01S4/00

CPC分类号： G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2272 ,  Y10T29/49002

摘要： This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.

摘要翻译： 本文件还讨论了包括主机控制器，输入/输出缓冲器和存储器件的系统。 存储器设备耦合到主机控制器，并被配置为从主机控制器接收读取命令。 非易失性包括与非易失性存储器通信的接口控制逻辑。 接口控制逻辑包括耦合到非易失性存储器和输入/输出缓冲器的等待时间编程电路。 延迟编程电路在读操作期间从非易失性存储器传送数据之前存储对应于要在非易失性存储器处提供的虚拟字节延迟的至少一个值。

公开(公告)号：US08208315B2

公开(公告)日：2012-06-26

申请号：US13052810

申请日：2011-03-21

申请人： Richard V. De Caro ,  Danut I Manea

发明人： Richard V. De Caro ,  Danut I Manea

IPC分类号： G11C16/04

CPC分类号： G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2272 ,  Y10T29/49002

摘要： This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.

摘要翻译： 本文件还讨论了包括主机控制器，输入/输出缓冲器和存储器件的系统。 存储器设备耦合到主机控制器，并被配置为从主机控制器接收读取命令。 非易失性包括与非易失性存储器通信的接口控制逻辑。 接口控制逻辑包括耦合到非易失性存储器和输入/输出缓冲器的等待时间编程电路。 延迟编程电路在读操作期间从非易失性存储器传送数据之前存储对应于要在非易失性存储器处提供的虚拟字节延迟的至少一个值。