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公开(公告)号：US20120256157A1
公开(公告)日：2012-10-11
申请号：US13528132
申请日：2012-06-20
IPC分类号： H01L47/00
CPC分类号： H01L47/00 , G11C13/0004 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
摘要翻译： 例如，一个存储单元被配置为使用两个存储单元晶体管和一个相变元件，通过将多个扩散层与位线平行地布置，在扩散层之间设置栅极以跨越位线，布置位 线接触和源触点交替地布置到针对每个扩散层的位线方向上的多个扩散层，以及在源极触点上提供相变元件。 此外，相位元件可以设置在位线触点上而不是源极触点。 通过这种方式，例如，可以实现存储单元晶体管的驱动性的提高和面积的减小。
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公开(公告)号：US20130105760A1
公开(公告)日：2013-05-02
申请号：US13719961
申请日：2012-12-19
IPC分类号： H01L47/00
CPC分类号： H01L47/00 , G11C13/0004 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
摘要翻译： 例如，一个存储单元被配置为使用两个存储单元晶体管和一个相变元件，通过将多个扩散层与位线平行地布置，在扩散层之间设置栅极以跨越位线，布置位 线接触和源触点交替地布置到针对每个扩散层的位线方向上的多个扩散层，以及在源极触点上提供相变元件。 此外，相位元件可以设置在位线触点上而不是源极触点。 通过这种方式，例如，可以实现存储单元晶体管的驱动性的提高和面积的减小。
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公开(公告)号：US20120097912A1
公开(公告)日：2012-04-26
申请号：US13345231
申请日：2012-01-06
IPC分类号： H01L45/00
CPC分类号： H01L47/00 , G11C13/0004 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
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公开(公告)号：US20110215288A1
公开(公告)日：2011-09-08
申请号：US13108174
申请日：2011-05-16
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675
摘要： Since a chalcogenide material has low adhesion to a silicon oxide film, there is a problem in that it tends to separate from the film during the manufacturing step of a phase change memory. In addition, since the chalcogenide material has to be heated to its melting point or higher during resetting (amorphization) of the phase change memory, there is a problem of requiring extremely large rewriting current. An interfacial layer includes an extremely thin insulator or semiconductor having the function as both an adhesive layer and a high resistance layer (thermal resistance layer) is inserted between chalcogenide material layer/interlayer insulative film and between chalcogenide material layer/plug.
摘要翻译： 由于硫族化物材料对氧化硅膜的粘附性低，所以存在在相变存储器的制造工序中与膜分离的问题。 此外，由于在相变存储器的复位（非晶化）期间必须将硫属化物材料加热至其熔点以上，所以存在需要非常大的重写电流的问题。 界面层包括极薄的绝缘体或半导体，具有将粘合剂层和高电阻层（热电阻层）两者插入到硫族化物材料层/层间绝缘膜之间以及硫族化物材料层/插塞之间的功能。
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公开(公告)号：US20090242868A1
公开(公告)日：2009-10-01
申请号：US12370417
申请日：2009-02-12
申请人： Kenzo KUROTSUCHI , Motoyasu TERAO , Norikatsu TAKAURA , Yoshihisa FUJISAKI , Kazuo ONO , Yoshitaka SASAGO
发明人： Kenzo KUROTSUCHI , Motoyasu TERAO , Norikatsu TAKAURA , Yoshihisa FUJISAKI , Kazuo ONO , Yoshitaka SASAGO
CPC分类号： H01L45/085 , H01L27/2436 , H01L27/2463 , H01L45/1233 , H01L45/1266 , H01L45/147 , H01L45/1625 , H01L45/1641
摘要： A solid electrolyte memory involves a problem that stable rewriting is difficult since the amount of ions in the solid electrolyte and the shape of the electrode are changed by repeating rewriting. In a semiconductor device in which information is stored or the circuit connection is changed by the change of resistance of the solid electrolyte layer, the solid electrolyte layer includes a composition, for example, of Cu—Ta—S and an ion supply layer in adjacent or close therewith as Cu—Ta—O, in which ions supplied from the ion supply layer form a conduction path in the solid electrolyte layer thereby making it possible to store information by the level of the resistance and applying the electric pulse to change the resistance, in which the ion supply layer includes crystals having, for example, a compositional ratio of: Cu—Ta—O=1:2:6 and rewriting operation can be performed stably.
摘要翻译： 固体电解质存储器存在难以稳定重写的问题，因为固体电解质中的离子量和电极的形状通过重复改写而改变。 在存储信息或通过固体电解质层的电阻变化来改变电路连接的半导体器件中，固体电解质层包括例如Cu-Ta-S的组合物和相邻的Cu-Ta-S的离子供给层 或与其接近的Cu-Ta-O，其中从离子供给层供给的离子在固体电解质层中形成传导路径，从而可以通过电阻水平存储信息并施加电脉冲以改变电阻 ，其中离子供给层包括例如以Cu-Ta-O = 1:2:6的组成比的晶体，并且可以稳定地进行重写操作。
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