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公开(公告)号：US20110153931A1
公开(公告)日：2011-06-23
申请号：US12644721
申请日：2009-12-22
IPC分类号： G06F12/08
CPC分类号： G06F17/30082 , G06F3/0611 , G06F3/064 , G06F3/0647 , G06F3/0685
摘要： A storage subsystem combining solid state drive (SSD) and hard disk drive (HDD) technologies provides low access latency and low complexity. Separate free lists are maintained for the SSD and the HDD and blocks of file system data are stored uniquely on either the SSD or the HDD. When a read access is made to the subsystem, if the data is present on the SSD, the data is returned, but if the block is present on the HDD, it is migrated to the SSD and the block on the HDD is returned to the HDD free list. On a write access, if the block is present in the either the SSD or HDD, the block is overwritten, but if the block is not present in the subsystem, the block is written to the HDD.
摘要翻译： 组合固态硬盘（SSD）和硬盘驱动器（HDD）技术的存储子系统提供低访问延迟和低复杂度。 为SSD保留独立的免费列表，HDD和文件系统数据块可以唯一存储在SSD或HDD上。 当对子系统进行读取访问时，如果SSD上存在数据，则返回数据，但是如果该块存在于HDD上，则迁移到SSD，并将HDD上的块返回到 硬盘免费列表。 在写访问中，如果该块存在于SSD或HDD中，则该块被覆盖，但是如果块不存在于子系统中，则该块被写入HDD。
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公开(公告)号：US08438334B2
公开(公告)日：2013-05-07
申请号：US12644721
申请日：2009-12-22
CPC分类号： G06F17/30082 , G06F3/0611 , G06F3/064 , G06F3/0647 , G06F3/0685
摘要： A storage subsystem combining solid state drive (SSD) and hard disk drive (HDD) technologies provides low access latency and low complexity. Separate free lists are maintained for the SSD and the HDD and blocks of file system data are stored uniquely on either the SSD or the HDD. When a read access is made to the subsystem, if the data is present on the SSD, the data is returned, but if the block is present on the HDD, it is migrated to the SSD and the block on the HDD is returned to the HDD free list. On a write access, if the block is present in the either the SSD or HDD, the block is overwritten, but if the block is not present in the subsystem, the block is written to the HDD.
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3.发明申请Technique for preserving memory affinity in a non-uniform memory access data processing system 审中-公开在不均匀的存储器访问数据处理系统中保存记忆亲和性的技术公开(公告)号：US20120198187A1
公开(公告)日：2012-08-02
申请号：US13015733
申请日：2011-01-28
CPC分类号： G06F9/5016 , G06F9/5088 , G06F2212/2542 , Y02D10/22 , Y02D10/32
摘要： Techniques for preserving memory affinity in a computer system is disclosed. In response to a request for memory access to a page within a memory affinity domain, a determination is made if the request is initiated by a processor associated with the memory affinity domain. If the request is not initiated by a processor associated with the memory affinity domain, a determination is made if there is a page ID match with an entry within a page migration tracking module associated with the memory affinity domain. If there is no page ID match, an entry is selected within the page migration tracking module to be updated with a new page ID and a new memory affinity ID. If there is a page ID match, then another determination is made whether or not there is a memory affinity ID match with the entry with the page ID field match. If there is no memory affinity ID match, the entry is updated with a new memory affinity ID; and if there is a memory affinity ID match, an access counter of the entry is incremented.
摘要翻译： 公开了一种用于在计算机系统中保存记忆亲和性的技术。 响应于对存储器相关域中的页面的存储器访问的请求，确定该请求是否由与存储器相关域相关联的处理器发起。 如果请求不是由与存储器相关性域相关联的处理器发起，则确定是否存在与存储器相关域相关联的页面迁移跟踪模块内的条目的页面ID匹配。 如果没有页面ID匹配，则在页面迁移跟踪模块中选择要更新新页面ID和新的内存关联ID的条目。 如果存在页面ID匹配，则另外确定存储器相关性ID是否与页面ID字段匹配的条目匹配。 如果没有内存关联ID匹配，则该条目将使用新的内存关联ID更新; 并且如果存在存储器相关性ID匹配，则增加该条目的访问计数器。
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4.发明授权公开(公告)号：US10169087B2
公开(公告)日：2019-01-01
申请号：US13015733
申请日：2011-01-28
摘要： Techniques for preserving memory affinity in a computer system is disclosed. In response to a request for memory access to a page within a memory affinity domain, a determination is made if the request is initiated by a processor associated with the memory affinity domain. If the request is not initiated by a processor associated with the memory affinity domain, a determination is made if there is a page ID match with an entry within a page migration tracking module associated with the memory affinity domain. If there is no page ID match, an entry is selected within the page migration tracking module to be updated with a new page ID and a new memory affinity ID. If there is a page ID match, then another determination is made whether or not there is a memory affinity ID match with the entry with the page ID field match. If there is no memory affinity ID match, the entry is updated with a new memory affinity ID; and if there is a memory affinity ID match, an access counter of the entry is incremented.
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公开(公告)号：US08751751B2
公开(公告)日：2014-06-10
申请号：US13015771
申请日：2011-01-28
CPC分类号： G06F12/0864 , G06F12/1018 , G06F12/1036
摘要： A method for minimizing cache conflict misses is disclosed. A translation table capable of facilitating the translation of a virtual address to a real address during a cache access is provided. The translation table includes multiple entries, and each entry of the translation table includes a page number field and a hash value field. A hash value is generated from a first group of bits within a virtual address, and the hash value is stored in the hash value field of an entry within the translation table. In response to a match on the entry within the translation table during a cache access, the hash value of the matched entry is retrieved from the translation table, and the hash value is concatenated with a second group of bits within the virtual address to form a set of indexing bits to index into a cache set.
摘要翻译： 公开了一种最小化缓存冲突漏洞的方法。 提供了一种能够有助于在高速缓存访问期间将虚拟地址转换为真实地址的转换表。 翻译表包括多个条目，并且翻译表的每个条目包括页码字段和散列值字段。 从虚拟地址内的第一组比特生成哈希值，并将哈希值存储在转换表内的条目的哈希值字段中。 响应于高速缓存访问期间在转换表内的条目的匹配，从转换表中检索匹配条目的散列值，并且将散列值与虚拟地址中的第二组位相连，以形成 一组索引位索引到高速缓存集中。
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公开(公告)号：US20130111135A1
公开(公告)日：2013-05-02
申请号：US13286507
申请日：2011-11-01
申请人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.
摘要翻译： 根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的系统和技术。 该系统包括处理器和高速缓存层级，其中高速缓存分层结构包括扇区高级缓存和未被覆盖的较低级高速缓存，并且其中高级高速缓存包括多个子扇区，每个子扇区具有高速缓存行大小 对应于较低级别缓存的高速缓存行大小。 该系统还包括可执行的逻辑，用于响应于确定来自较高级别高速缓存的高速缓存线将被驱逐到较低级高速缓存：识别要驱逐的高速缓存行的参考子扇区; 使缓存行的未引用子扇区无效; 并将参考的子扇区存储在较低级别的高速缓存中。
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7.发明授权Performance of emerging applications in a virtualized environment using transient instruction streams 有权使用瞬态指令流在虚拟化环境中的新兴应用程序的性能公开(公告)号：US09323527B2
公开(公告)日：2016-04-26
申请号：US12905208
申请日：2010-10-15
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.
摘要翻译： 公开了用于管理瞬时指令流的方法，系统和计算机可用介质。 在已知很少执行的分支和链路（BRL）指令中定义了瞬态标志。 在执行指令请求线程的硬件（例如，核心）的专用寄存器（SPR）中同样设置一个位。 请求线程中的后续提取或预取将被视为暂时的，并且不会写入低级缓存。 如果指令是非瞬态的，并且如果低级缓存不包括L1指令高速缓存，则从存储器获得的获取或预取缺失可以被写入L1和下级高速缓存中。 如果不包括在内，则可以将低速缓存中的L1指令高速缓存中的退出写入。
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公开(公告)号：US20120096240A1
公开(公告)日：2012-04-19
申请号：US12905176
申请日：2010-10-15
CPC分类号： G06F9/505 , G06F12/0862 , G06F2209/503 , G06F2212/6026
摘要： A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.
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公开(公告)号：US08935478B2
公开(公告)日：2015-01-13
申请号：US13286507
申请日：2011-11-01
申请人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.
摘要翻译： 根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的系统和技术。 该系统包括处理器和高速缓存层级，其中高速缓存分层结构包括扇区高级缓存和未被覆盖的较低级高速缓存，并且其中高级高速缓存包括多个子扇区，每个子扇区具有高速缓存行大小 对应于较低级别缓存的高速缓存行大小。 该系统还包括可执行的逻辑，用于响应于确定来自较高级别高速缓存的高速缓存线将被驱逐到较低级高速缓存：识别要驱逐的高速缓存行的参考子扇区; 使缓存行的未引用子扇区无效; 并将参考的子扇区存储在较低级别的高速缓存中。
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公开(公告)号：US08782346B2
公开(公告)日：2014-07-15
申请号：US13586518
申请日：2012-08-15
IPC分类号： G06F12/08
CPC分类号： G06F12/0815
摘要： Some embodiments of the inventive subject matter are directed to determining that a memory access request results in a cache miss and determining an amount of cache resources used to service cache misses within a past period in response to determining that the memory access request results in the cache miss. Some embodiments are further directed to determining that servicing the memory access request would increase the amount of cache resources used to service cache misses within the past period to exceed a threshold. In some embodiments, the threshold corresponds to reservation of a given amount of cache resources for potential cache hits. Some embodiments are further directed to rejecting the memory access request in response to the determining that servicing the memory access request would increase the amount of cache resources used to service cache misses within the past period to exceed the threshold.
摘要翻译： 本发明的一些实施例涉及确定存储器访问请求导致高速缓存未命中，并且响应于确定存储器访问请求导致高速缓存而确定用于在过去时段内服务高速缓存未命中的高速缓存资源量 小姐。 一些实施例进一步涉及确定对存储器访问请求的服务将增加用于在过去时间段内服务高速缓存未命中的高速缓存资源的数量超过阈值。 在一些实施例中，阈值对应于用于潜在高速缓存命中的给定量的高速缓存资源的预留。 响应于确定对存储器访问请求的服务会增加在过去时间段内用于服务高速缓存未命中的高速缓存资源的数量超过阈值，一些实施例进一步涉及拒绝存储器访问请求。
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