公开(公告)号：US5089722A

公开(公告)日：1992-02-18

申请号：US503012

申请日：1990-04-02

申请人： Robert J. Amedeo

发明人： Robert J. Amedeo

IPC分类号： H03K17/16 ,  H03K17/687

CPC分类号： H03K17/6872 ,  H03K17/164

摘要： A pre-driver stage includes two pairs of series-stacked transistors for responding to input stage outputs and provides first and second outputs to an output driver stage. The first output becomes low at a certain delay period after the second output becomes low, and the second output becomes high at a certain delay period after the first output becomes high. Therefore, the turn-off of the active driver transistor is completed before the turn-on of the opposite output transistor, inhibiting an overlap current. In another form, the buffer circuit also uses assist transistors placed near the driver transistors for assisting the opposite driver transistors in turning off.

摘要翻译： 预驱动器级包括两对串联堆叠的晶体管，用于响应于输入级输出，并向输出驱动级提供第一和第二输出。 在第二输出变为低电平之后的第一输出在一定的延迟时间内变低，第二输出在第一输出变为高电平之后的特定延迟时段变为高电平。 因此，有源驱动晶体管的截止在相反的输出晶体管的导通之前完成，从而抑制重叠电流。 在另一种形式中，缓冲电路还使用放置在驱动晶体管附近的辅助晶体管来辅助相反的驱动晶体管关断。

公开(公告)号：US20090189636A1

公开(公告)日：2009-07-30

申请号：US12022199

申请日：2008-01-30

申请人： Robert J. Amedeo ,  Christopher K.Y. Chun

发明人： Robert J. Amedeo ,  Christopher K.Y. Chun

IPC分类号： H03K19/003

CPC分类号： H03K19/0016

摘要： A storage circuit has an input for receiving and storing data, a first power terminal coupled to a first conductor for receiving a first power supply voltage, and a second power terminal coupled to a second conductor. A power gate device has a first terminal coupled to the second conductor, a control terminal for receiving a bias voltage in response to a control signal, and a second terminal coupled to a terminal for receiving a second power supply voltage. A shorting device selectively electrically short circuits the first terminal of the power gate device to the control terminal of the power gate device in response to the control signal, thereby converting the power gate device from a transistor into a diode-connected device. The shorting device is smaller in size than the power gate device.

摘要翻译： 存储电路具有用于接收和存储数据的输入端，耦合到用于接收第一电源电压的第一导体的第一电源端子和耦合到第二导体的第二电源端子。 功率门装置具有耦合到第二导体的第一端子，用于响应于控制信号接收偏置电压的控制端子，以及耦合到端子的用于接收第二电源电压的第二端子。 短路装置响应于控制信号选择性地将电力门装置的第一端子短路到电力门装置的控制端子，从而将电源栅极装置从晶体管转换成二极管连接的装置。 短路装置的尺寸小于电源门装置。

公开(公告)号：US07619440B2

公开(公告)日：2009-11-17

申请号：US12022199

申请日：2008-01-30

申请人： Robert J. Amedeo ,  Christopher K. Y. Chun

发明人： Robert J. Amedeo ,  Christopher K. Y. Chun

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0016

摘要： A storage circuit has an input for receiving and storing data, a first power terminal coupled to a first conductor for receiving a first power supply voltage, and a second power terminal coupled to a second conductor. A power gate device has a first terminal coupled to the second conductor, a control terminal for receiving a bias voltage in response to a control signal, and a second terminal coupled to a terminal for receiving a second power supply voltage. A shorting device selectively electrically short circuits the first terminal of the power gate device to the control terminal of the power gate device in response to the control signal, thereby converting the power gate device from a transistor into a diode-connected device. The shorting device is smaller in size than the power gate device.

摘要翻译： 存储电路具有用于接收和存储数据的输入端，耦合到用于接收第一电源电压的第一导体的第一电源端子和耦合到第二导体的第二电源端子。 功率门装置具有耦合到第二导体的第一端子，用于响应于控制信号接收偏置电压的控制端子，以及耦合到端子的用于接收第二电源电压的第二端子。 短路装置响应于控制信号选择性地将电力门装置的第一端子短路到电力门装置的控制端子，从而将电源栅极装置从晶体管转换成二极管连接的装置。 短路装置的尺寸小于电源门装置。

公开(公告)号：US5325341A

公开(公告)日：1994-06-28

申请号：US936989

申请日：1992-08-31

申请人： J. Greg Viot ,  Robert J. Amedeo ,  Nancy L. Thomas ,  Marc L. DeWever ,  Dale J. Kumke ,  Everett R. Lumpkin

发明人： J. Greg Viot ,  Robert J. Amedeo ,  Nancy L. Thomas ,  Marc L. DeWever ,  Dale J. Kumke ,  Everett R. Lumpkin

IPC分类号： G04F10/04 ,  G04F8/00 ,  G06F1/04

CPC分类号： G04F10/04

摘要： A digital timer apparatus incorporates a free running counter, an interval timer, a capture register, a pulse accumulator; holding logic and mode selection logic. In one mode of operation, a rising or falling edge of an external signal causes the current contents of the free running counter to be loaded into the capture register, causes the previous value of the capture register to be transferred to a holding register and causes the pulse accumulator to be incremented. A read of the capture holding register causes the pulse accumulator value to be transferred to a holding register and causes the pulse accumulator to be reset. The output of the interval timer can cause an interrupt signal to be generated to request service from a central processing unit. The timer apparatus is particularly well suited to performing tasks related to the determination of the speed of rotation of a rotating member and may be used, for instance, in detecting wheel rotational speeds in an anti-lock brake system or detecting shaft rotation speeds in an automatic transmission.

摘要翻译： 数字定时器装置包括自由运行计数器，间隔定时器，捕获寄存器，脉冲累加器; 保持逻辑和模式选择逻辑。 在一种操作模式中，外部信号的上升或下降沿使自由运行计数器的当前内容加载到捕捉寄存器中，使得捕获寄存器的先前值被传送到保持寄存器，并导致 脉冲累加器增加。 捕获保持寄存器的读取将脉冲累加器值传送到保持寄存器，并使脉冲累加器复位。 间隔定时器的输出可以产生中断信号以从中央处理单元请求服务。 定时器装置特别适合于执行与确定旋转部件的旋转速度有关的任务，并且可以用于例如在防抱死制动系统中检测轮转速或检测轴转速 自动变速器。

公开(公告)号：US5301335A

公开(公告)日：1994-04-05

申请号：US907077

申请日：1992-07-01

申请人： John A. Langan ,  Robert J. Amedeo ,  Nancy L. Thomas

发明人： John A. Langan ,  Robert J. Amedeo ,  Nancy L. Thomas

IPC分类号： G06F13/24 ,  G06F13/00

CPC分类号： G06F13/24

摘要： A register having a selective wait feature includes logic for receiving a new value to be stored and logic for selectively delaying the appearance of the new value at the output of the register until some predetermined event has occurred. The register can also be read to determine whether the event has occurred. The register is disclosed in the context of a microprocessor-controlled digital timer apparatus which responds to an incoming pulse train. Certain control bits in the apparatus determine whether the digital timer is responsive to rising edges of the pulse train, falling edges, any edges, or no edges. The microprocessor determines, at the time new values are stored to those control bit locations, whether the new values are to become effective immediately or are to be delayed until some intervening event has occurred. The register permits control over the time at which transitions between different operating modes are made in order to assure orderly operation.

摘要翻译： 具有选择性等待特征的寄存器包括用于接收要存储的新值的逻辑和用于选择性地延迟寄存器输出处的新值的出现的逻辑，直到出现一些预定事件。 也可以读取寄存器以确定事件是否发生。 该寄存器在响应输入脉冲串的微处理器控制的数字定时器装置的上下文中公开。 设备中的某些控制位确定数字定时器是否响应于脉冲串的上升沿，下降沿，任何边缘或无边缘。 微处理器在将新值存储到那些控制位位置时确定新值是否立即生效或者被延迟直到发生了一些中间事件。 寄存器允许控制在不同操作模式之间进行转换的时间，以确保有序操作。

公开(公告)号：US5293628A

公开(公告)日：1994-03-08

申请号：US787167

申请日：1991-11-04

申请人： John A. Langan ,  Robert J. Amedeo ,  Roberto M. Frontera

发明人： John A. Langan ,  Robert J. Amedeo ,  Roberto M. Frontera

IPC分类号： H03K5/05 ,  G06F1/025 ,  G06F1/04

CPC分类号： G06F1/025

摘要： A data processing system (10) capable of generating an output waveform (22) that has enhanced pulse width resolution. In one form, the system uses a counter (34) which is incremented by an input clock (20) running at an operating frequency of the system. Instead of incrementing the counter (34) by one, the counter (34) is incremented by a power of two so that the counter (34) appears to be counting a power of two faster. However, in order to increase the effective resolution of the counter (34), the second edge of the output waveform (22) must be correctly adjusted depending on the desired duty cycle and period. The end result is a counter (34) that can produce a power of two greater resolution while still using the operating frequency of the system as an input clock (20).

摘要翻译： 一种能够产生具有增强的脉冲宽度分辨率的输出波形（22）的数据处理系统（10）。 在一种形式中，系统使用计数器（34），计数器（34）由以系统的工作频率运行的输入时钟（20）递增。 而不是将计数器（34）递增一个，计数器（34）增加2的幂，使得计数器（34）似乎计数得更快的功率。 然而，为了增加计数器（34）的有效分辨率，输出波形（22）的第二边缘必须根据期望的占空比和周期被正确地调整。 最终的结果是可以产生两个较高分辨率的功率的计数器（34），同时仍然使用系统的工作频率作为输入时钟（20）。

公开(公告)号：US5233573A

公开(公告)日：1993-08-03

申请号：US986195

申请日：1992-12-07

申请人： Rudolf Bettelheim ,  Robert J. Amedeo ,  John A. Langan

发明人： Rudolf Bettelheim ,  Robert J. Amedeo ,  John A. Langan

IPC分类号： G06F1/14

CPC分类号： G06F1/14

摘要： A digital timer apparatus incorporates a free running counter, an interval timer, a capture register, a pulse accumulator and holding logic. A rising or falling edge of an external signal causes the current contents of the free running counter to be loaded into the capture register and causes the pulse accumulator to be incremented. The output of the interval timer can cause the contents of the pulse accumulator and capture register to be stored into the holding logic. The timer apparatus is particularly well suited to performing tasks related to the determination of the speed of rotation of a rotating member and may be used, for instance, in detecting wheel rotational speeds in an anti-lock brake system or detecting shaft rotation speeds in an automatic transmission.

摘要翻译： 数字定时器装置包括自由运行计数器，间隔定时器，捕获寄存器，脉冲累加器和保持逻辑。 外部信号的上升沿或下降沿使自由运行计数器的当前内容加载到捕捉寄存器中，并使脉冲累加器递增。 间隔定时器的输出可以使脉冲累加器和捕捉寄存器的内容存储在保持逻辑中。 定时器装置特别适合于执行与确定旋转部件的旋转速度有关的任务，并且可以用于例如在防抱死制动系统中检测轮转速或检测轴转速 自动变速器。