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    RC-Triggered Power Clamp Suppressing Negative Mode Electrostatic Discharge Stress
    1.
    发明申请
    RC-Triggered Power Clamp Suppressing Negative Mode Electrostatic Discharge Stress 失效
    RC触发电源钳位抑制负模式静电放电应力

    公开(公告)号：US20070285853A1

    公开(公告)日：2007-12-13

    申请号：US11422608

    申请日：2006-06-07

    申请人： Robert J. Gauthier ,  Dimitrios K. Kontos ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    发明人： Robert J. Gauthier ,  Dimitrios K. Kontos ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    IPC分类号： H02H9/00

    CPC分类号： H02H9/046

    摘要： An electrostatic discharge (ESD) power clamp circuit including a RC-delay element coupled to a plurality of serialized inverter elements with a power clamp element and an ESD-triggered keeper device coupled to the plurality of inverters. During negative mode ESD events, the ESD-triggered keeper device is activated and assists the power clamp element to pull up and strongly conduct current to protect the circuit. Additionally, a method of ESD protection in a circuit is provided. The method includes coupling a RC-delay element to an input of a plurality of serialized inverter elements, coupling an output of the plurality of serialized inverters with an ESD-triggered keeper device and a power clamp element, triggering the ESD-triggered keeper device to turn on during negative ESD events and conducting current by the power clamp element with assistance of the ESD-triggered keeper device to protect the circuit as a result of negative ESD events.

    摘要翻译： 一种静电放电（ESD）功率钳位电路，其包括耦合到多个串联反相器元件的RC延迟元件，其具有耦合到所述多个逆变器的功率钳位元件和ESD触发的保持器装置。 在负模式ESD事件期间，ESD触发的保护装置被激活，并且帮助电源钳位元件上拉并强烈地传导电流以保护电路。 另外，提供了电路中ESD保护的方法。 该方法包括将RC延迟元件耦合到多个串联反相器元件的输入端，将多个串联反相器的输出与ESD触发的保持器装置和功率钳位元件耦合，将ESD触发的保持器装置触发 在ESD ESD事件期间接通电源，并通过ESD触发的保护装置的辅助，通过电源钳位元件传导电流，以保护电路由于负ESD事件。

    RC-triggered power clamp suppressing negative mode electrostatic discharge stress
    2.
    发明授权
    RC-triggered power clamp suppressing negative mode electrostatic discharge stress 失效
    RC触发功率钳位抑制负模式静电放电应力

    公开(公告)号：US07518845B2

    公开(公告)日：2009-04-14

    申请号：US11422608

    申请日：2006-06-07

    申请人： Robert J. Gauthier, Jr. ,  Dimitrios K. Kontos ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    发明人： Robert J. Gauthier, Jr. ,  Dimitrios K. Kontos ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    IPC分类号： H02H9/00 ,  H02H1/00

    CPC分类号： H02H9/046

    摘要： An electrostatic discharge (ESD) power clamp circuit including a RC-delay element coupled to a plurality of serialized inverter elements with a power clamp element and an ESD-triggered keeper device coupled to the plurality of inverters. During negative mode ESD events, the ESD-triggered keeper device is activated and assists the power clamp element to pull up and strongly conduct current to protect the circuit. Additionally, a method of ESD protection in a circuit is provided. The method includes coupling a RC-delay element to an input of a plurality of serialized inverter elements, coupling an output of the plurality of serialized inverters with an ESD-triggered keeper device and a power clamp element, triggering the ESD-triggered keeper device to turn on during negative ESD events and conducting current by the power clamp element with assistance of the ESD-triggered keeper device to protect the circuit as a result of negative ESD events.

    摘要翻译： 一种静电放电（ESD）功率钳位电路，其包括耦合到多个串联反相器元件的RC延迟元件，其具有耦合到所述多个逆变器的功率钳位元件和ESD触发的保持器装置。 在负模式ESD事件期间，ESD触发的保护装置被激活，并且帮助电源钳位元件上拉并强烈地传导电流以保护电路。 另外，提供了电路中ESD保护的方法。 该方法包括将RC延迟元件耦合到多个串联反相器元件的输入端，将多个串联反相器的输出与ESD触发的保持器装置和功率钳位元件耦合，将ESD触发的保持器装置触发 在ESD ESD事件期间接通电源，并通过ESD触发的保护装置的辅助，通过电源钳位元件传导电流，以保护电路由于负ESD事件。

    RC-triggered semiconductor controlled rectifier for ESD protection of signal pads
    3.
    发明授权
    RC-triggered semiconductor controlled rectifier for ESD protection of signal pads 有权
    RC触发半导体可控整流器用于信号焊盘的ESD保护

    公开(公告)号：US08891212B2

    公开(公告)日：2014-11-18

    申请号：US13079946

    申请日：2011-04-05

    申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    IPC分类号： H02H9/04 ,  H03K19/003 ,  H01L27/02

    CPC分类号： H02H9/046 ,  H01L27/0262 ,  H03K19/00361 ,  Y10T29/49002

    摘要： RC-trigger circuits for a semiconductor controlled rectifier (SCR), methods of providing electrostatic discharge (ESD) protection, and design structures for a RC-trigger circuit. The RC-trigger circuit is coupled to an input/output (I/O) signal pad by an isolation diode and is coupled to a power supply voltage by a power supply diode. Under normal operating conditions, the isolation diode is reverse biased, isolating the RC-trigger circuit from the input/output (I/O) pad, and the power supply diode is forward biased so that the RC-trigger circuit is supplied with power. The isolation diode may become forward biased during ESD events while the chip is unpowered, causing the RC-trigger circuit to trigger an SCR configured protect the signal pad from ESD into a conductive state. The power supply diode may become reverse biased during the ESD event, which isolates the power supply rail from the ESD voltage pulse.

    摘要翻译： 用于半导体可控整流器（SCR）的RC触发电路，提供静电放电（ESD）保护的方法以及用于RC触发电路的设计结构。 RC触发电路通过隔离二极管耦合到输入/输出（I / O）信号焊盘，并通过电源二极管耦合到电源电压。 在正常工作条件下，隔离二极管反向偏置，将RC触发电路与输入/输出（I / O）焊盘隔离，电源二极管正向偏置，使RC触发电路供电。 在ESD事件期间，隔离二极管可能会在芯片未上电时产生正向偏置，导致RC触发电路触发SCR配置，从而将信号焊盘从ESD保护到导通状态。 在ESD事件期间，电源二极管可能会反向偏置，从而将电源轨与ESD电压脉冲隔离。

    Design structures for high-voltage integrated circuits
    4.
    发明授权
    Design structures for high-voltage integrated circuits 失效
    高压集成电路的设计结构

    公开(公告)号：US07786535B2

    公开(公告)日：2010-08-31

    申请号：US12059034

    申请日：2008-03-31

    申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

    发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

    IPC分类号： H01L29/78

    CPC分类号： H01L27/1203

    摘要： Design structures for high-voltage integrated circuits. The design structure, which is formed using a semiconductor-on-insulator (SOI) substrate, may include device structure with a semiconductor body positioned between first and second gate electrodes. The first and second gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the first and second gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrently with a process forming other device isolation regions.

    摘要翻译： 高压集成电路的设计结构。 使用绝缘体上半导体（SOI）衬底形成的设计结构可以包括具有位于第一和第二栅电极之间的半导体本体的器件结构。 第一和第二栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。 电介质层将第一和第二栅极电极与半导体本体分开。 这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，介电材料可与形成其它器件隔离区的工艺同时进行。

    VERTICAL CURRENT CONTROLLED SILICON ON INSULATOR (SOI) DEVICE SUCH AS A SILICON CONTROLLED RECTIFIER AND METHOD OF FORMING VERTICAL SOI CURRENT CONTROLLED DEVICES
    7.
    发明申请
    VERTICAL CURRENT CONTROLLED SILICON ON INSULATOR (SOI) DEVICE SUCH AS A SILICON CONTROLLED RECTIFIER AND METHOD OF FORMING VERTICAL SOI CURRENT CONTROLLED DEVICES 有权
    绝缘体（SOI）器件上的垂直电流控制硅如硅控制整流器及形成垂直SOI电流控制器件的方法

    公开(公告)号：US20080308837A1

    公开(公告)日：2008-12-18

    申请号：US11762811

    申请日：2007-06-14

    申请人： Robert J. Gauthier, JR. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher S. Putnam

    发明人： Robert J. Gauthier, JR. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher S. Putnam

    IPC分类号： H01L29/74 ,  H01L21/20 ,  H01L21/332 ,  H01L21/84 ,  H01L29/00

    CPC分类号： H01L27/0262

    摘要： A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.

    摘要翻译： 具有诸如垂直硅控制整流器（SCR），垂直双极晶体管，垂直电容器，电阻器和/或垂直钳位电阻器等器件的绝缘体硅（SOI）集成电路（IC）芯片及其制造方法 s）。 器件通过SOI表面层和绝缘体层形成在晶种孔中。 通过衬底中的种子孔形成例如N型的掩埋扩散。 掺杂的外延层形成在掩埋扩散层上，并且可以包括多个掺杂层，例如P型层和N型层。 可以在掺杂的外延层上形成多晶硅，例如P型。 与埋入扩散部的接触形成在接触衬里中。

    Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures
    9.
    发明授权
    Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures 有权
    用于高压引脚ESD保护的双向背对背堆叠SCR，制造和设计结构的方法

    公开(公告)号：US08503140B2

    公开(公告)日：2013-08-06

    申请号：US12898013

    申请日：2010-10-05

    申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0262 ,  H01L29/747 ,  H01L29/87 ,  H02H9/04

    摘要： Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode of a first of the back-to-back stacked SCR is connected to an input. An anode of a second of the back-to-back stacked SCR is connected to ground. Cathodes of the first and second of the back-to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively and deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.

    摘要翻译： 提供用于高压针ESD保护的双向背对背堆叠SCR，制造方法和设计结构。 该器件包括对称双向背对背层叠可控硅整流器（SCR）。 背对背堆叠的SCR中的第一个的阳极连接到输入。 背对背堆叠的SCR的第二个的阳极连接到地面。 第一个和第二个背靠背堆叠的SCR的阴极连接在一起。 对称双向背靠背SCR中的每一个包括一对二极管，其引导电流朝向阴极，其在施加电压时有效地变得有效地反向偏置，并且从对称的双向后向SCR中的一个去激活元件， 另一个对称双向背对背SCR的二极管在与反向偏置二极管相同的方向上直流电流，反向SCR。

    SEMICONDUCTOR-ON-INSULATOR DEVICE WITH ASYMMETRIC STRUCTURE
    10.
    发明申请
    SEMICONDUCTOR-ON-INSULATOR DEVICE WITH ASYMMETRIC STRUCTURE 有权
    具有不对称结构的半导体绝缘体器件

    公开(公告)号：US20120187525A1

    公开(公告)日：2012-07-26

    申请号：US13012137

    申请日：2011-01-24

    申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    IPC分类号： H01L29/12 ,  G06F17/50 ,  H01L21/36

    CPC分类号： H01L27/0255 ,  G06F17/5022 ,  G06F17/5045 ,  H01L27/0262 ,  H01L27/1203 ,  H01L29/6609 ,  H01L29/66393 ,  H01L29/7436 ,  H01L29/861

    摘要： Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.

    摘要翻译： 在SOI工艺中具有减小的结面积的器件结构，制造器件结构的方法以及横向二极管的设计结构。 器件结构包括位于器件区域中并与阳极和阴极之间的p-n结相交的一个或多个电介质区域，例如STI区域。 可以使用浅沟槽隔离技术形成的电介质区域用于在p-n结和阳极侧向间隔的位置处减小p-n结相对于阴极宽度区域的宽度。 介质区域的宽度差和存在产生不对称二极管结构。 由电介质区域占据的器件区域的体积被最小化以保持阴极和阳极的体积。